Fpga spi veriloglavori
...devices. If this task is not OK we will stop here and cancel the project!!! Task 2 - - - - - - - - - - Integration of some sensor (SHT31 or PIR detector) in order to test the network devices. Implement Remote rele activation using GPIO25 in End node. Comand for activation will be provided from Coordinator. //I2C pins #define I2C_SDA_2 33 #define I2C_SCL_2 32 //SDCARD pins (SPI pins) #define SPI_CLK 18 #define SPI_MISO 19 #define SPI_MOSI 23 #define SPI_SS 5 Optional: Hibernate to be integrated in the end node device. I can help you with this task. Task 3 - - - - - - - - - - If data can not be sent to coordinator, due to coordinator is down, save the data on SD card (unsend,txt file) and send it when coordinator...
Hi Olufunmi F., I noticed your profile and would like to offer you my project. We can discuss any details over chat. have you done any work on qam / ofdm / ofdm-im implemenation on fpga
Hi Quan D., I noticed your profile and would like to offer you my project. We can discuss any details over you done any work on qam / ofdm / ofdm-im implemenation on fpga
Hi Oleg K., I noticed your profile and would like to offer you my project. We can discuss any details over chat. have you done any work on qam / ofdm / ofdm-im implemenation on fpga
Hi Eren K., I noticed your profile and would like to offer you my project. We can discuss any details over chat. have you done any work on qam / ofdm / ofdm-im implemenation on fpga
Hi George Z., I noticed your profile and would like to offer you my project. We can discuss any details over chat. have you done any work on qam / ofdm / ofdm-im implemenation on fpga
Hi Rajagopal S., I noticed your profile and would like to offer you my project. We can discuss any details over chat. have you done any work on qam / ofdm / ofdm-im implemenation on fpga
Hi Aamir Sohail N., I noticed your profile and would like to offer you my project. We can discuss any details over chat. have you done any work on qam / ofdm / ofdm-im implemenation on fpga
Hi Muhammad H., I noticed your profile and would like to offer you my project. We can discuss any details over chat. have you done any work on qam / ofdm / ofdm-im implemenation on fpga
Hi Muhammad T., I noticed your profile and would like to offer you my project. We can discuss any details over chat. have you done any work on qam / ofdm / ofdm-im implemenation on fpga
Hi Muhammad Huzaifa R., I noticed your profile and would like to offer you my project. We can discuss any details over chat. have you done any work on qam / ofdm / ofdm-im implemenation on fpga
Hi Dhivagar E., I noticed your profile and would like to offer you my project. We can discuss any details over you done any work on qam / ofdm / ofdm-im implemenation on fpga
Need to develop a small module(Hardware and embedded software) for Universal RFID reader. Module must: Work with 2 antennas 13.56Mhz and 125Khz. Support work with main RFID formats: MIFARE, EMMARINE, NFC, HID, INDALA, AWID Support work with APDU command to work with phone NFC (IOS, Support work with ANDROID) to read card data by GPAY or Apple pay. Support work with the main MCU by the SPI bus. Support work with power not more than 5VDC The module must have next pins: Reset, Sleep, Find RFID Module size not more than 20x30 mm (without antenna)
>Registrati o accedi per visualizzare i dettagli.
...0-100%. Depending on an analog signal that will be acquired through an adc spi connected chip, the program will go into different states. When a specified state is reached, there needs to be communication with a QCA7000 chip (power line communication) which will in turn talk to an external device. 1) The communication with the external device needs to be via a local network that has to be set up with the slac protocol. When this network has been set up, there needs to be communication between the QCA7000 chip and the external device. The data between these devices needs to be formatted using the DIN and/or ISO norm. 2) There will also be a program to send and read digital I/O as well as communicate through spi to a CAN chip. 3) Both these programs need to be...
I need to write a code for a NodeMCU to connect to Blynk. The components in the system are as following: 2 IR E18-D80NK (IRSensor_1 & IRSensor_2) 2 Relay Modules (PumpRelay_1 & Pump_Relay2) 1 Ws2812 x24 Neopixel compatible (Led) 1 Push Button 1 1.44" TFT SPI Display The IR and Relay works as an independent system. Whenever IRSensor_1 detects and objetc (Serial print: "Hand detected"), send a signal and activate PumpRelay_1 for 0.5 seconds (Serial print: "Activating hand sanitizer relay pump"). After that, dont send any signals to the Relay for 2 seconds and add +1 to the counter of the Relay (Serial print: "Hand sanitizer has been activated X amount of times"). Whenever IRSensor_2 detects and objetc (Serial print: "Foot detected&quo...
Hello! I want to Implement a signal synthesizer, for that i need some sort of code and simulation where i give a sine wave as an input to an ADC where it is converted into digital form and from there the signal is passed to the FPGA where it can be synthesized, I have 2 effects that i want to apply on that signal. Ill provide those to you, and then i want to show the output using a DAC. I have the MAX 10 neek but i only need a simulation on a computer. I dont want to actually implement it on the board PLEASE SEE ATTACHMENTS TO SEE THE TWO FILTERS
Hi Saddam G., I noticed your profile and would like to offer you my project. We can discuss any details over chat. have you done any work on qam / ofdm / ofdm-im implemenation on fpga
Hello Mam, I need your guidance for good practicing of verilog for my career .
First step: implementation of dcStep function. - Communication and control over SPI (not DIR and STEP) - Auto tuning routine with seral output of all relevant values - Set the function “dcStep” by call one attribute in the main loop - Possibility to change the max. current, speed, duration… in the loop+
We want to implement Bit coin mining Beam algorithm on FPGA board.
Design I2C HDL module to send start-up command sequence to ADV7511 HDMI transmitter upon system power-up. All hardware is already setup on a Spartan-7 FPGA development board and ready for test. Video requirements and all documentation will be provided. Do you have experience with any ADV IC's? What is your experience with FPGA's/Verilog?
Hi there. I need some C Firmware coding of nRF52832 SoC. The feature consist of mainly: - Enhanced Shock-Burst - UART - Custom SPI Link (GPIO based Logic Analyzer Data Send Receive) - OTA-DFU etc. Developer having multiple nRF52832 Boards will be a very big plus for testing and debugging. Highly preferred freelancer from China/HK. Thanks.
Design a vending machine in Verilog I need it to be in verilog language
I need test program for DE10-Lite board for UART communication. if you have experience, you can work remotely on my pc what was connected with the board. Quartus 18 was installed already with USB-UART converter. Bid on this project if you can do this. #1. Nios 2 UART test #2. communication with MCU (MCU part firmware prepared)
hi Need to a test program Nios II for UART communication. It should be run on DE10-Lite kit with Quartus 18.1 Hope to keep the relation with experienced developer. With the experienced developer, I will move forward one by one, Thanks
Verilog implementation of an encoding algorithm that has a text file as an input and uses unused ascii characters to replace frequent occurring words. I can share the research paper, I need this done in a very short time of about less than 5 days
i need need bitstreams made for zhash running at 1000.0 hashrate and zcash running at 1000 hashrate basically multiple bitstreams that can run high hashrate but deal out low power attage on bcu1525 fpgas no more than 350 watts each card
...C/C++ project, not interpreted Python or Java. I promise this needs some serious embedded Pi / C experience. Lots or SPI/I2C, data manipulation, comms and an near real time. This isn’t 95% project. Existing controllers have >1year uptimes. Original post... Looking to engage an advanced C developer that is familiar and productive in these areas... I expect this will be around six weeks of work to reach v0.1 EMBEDDED LINUX, custom hardware Key points in no particular order... Willing to be flexible during discovery phase! Raspberry Pi - specifically ZERO W at the moment on custom SMT boards. Added hardware I/O elements C/C++ coding, not Java or Python Real-time operation SPI & I2C on multiple devices Non-blocking asynchronous code methods Familiarity with S...
I need the code development using ATMEGA328p, 23LC1024 SRAM and FLASH SPI memory to store data permantly every hour for 3 years. Data consist in: -Date/hour (RTC DS3231) - 1 float - 1 long No need hardware or PCB design. Thanks
...absolutely necessary to go 0402. I anticipate the design will fit into 100x50mm. - F9P UBlox receiver with SMA connector and appropriately designed 50 ohm RF antenna trace w/ shielding. All IOs connected to MCU. note: this connects to an L1 and L2 dual band antenna - microSD card socket connected to MCU via SDIO (e.g. MEM2067). Include card-detect pin. - 3 x IMU sensors (ICM-20948) connected by single SPI from MCU plus. Al IO inc interrupts - RJ45 magnetic socket with appropriate phy/transceiver connected to MCU - 25MHz HSE oscillator (assumed to be required for ETH) - STLink / 3-wire debug and headers - 12-20V DC source. Power regulation and filtering as appropriate. (e.g. 5V SMPS with appropriate filters to minimise P2P ripple then a series of 3.3V and maybe 1.8V LDO for...
Hi Junaid A., how are you friend!! I'm studing a project based in FPGA SoC..... Can we talk about it. Im from Brazil.
Hi there We have a ready PCB design (used DipTrace software) but we need to make changes, all of those changes described in document, there are also ready examples of each modification you only need to add them to the design, what we need: -Change traces -Add additional trace (like SPI/UART) -Add/Remove pins -Check components, like if they are too weak or incompatible
- Long term assignmen...engineer will work with a team of specialists who will be responsible for developing, testing, and supporting electronics boards or sub-systems. - The engineer will define electrical and test requirements, design circuits and test equipment. Required Skills: One or more of the following skills are needed. Digital Design: - Design of digital data acquisition system; - VHDL embedded code for FPGA logic; - A/D and or D/A; - Testing Validation and Verification (V&V) of requirements. Analog Design: - Low noise analog interface for sensor application; photonics sensors; - Power amplifier design (motors / actuators); - Capacitance gauge, LVDT interface design; - A/D and or D/A; - Testing Validation and Verification (V&V) of requirements - H...
Hi there We have a ready PCB design (used DipTrace software) but we need to make changes, all of those changes described in document, there are also ready examples of each modification you only need to add them to the design, what we need: -Change traces -Add additional trace (like SPI/UART) -Add/Remove pins -Check components, like if they are too weak or incompatible
We have written a code in C language for a microcontroller from Nuvoton , which has an ARM Cortex M4 core. Essentislly , the microcontroller is connected to three multi-channel simultaneously sampling sigma-delta conver...We suspect our algorithms and code ( all in C ) , though proven for functionality , need to be optimised ( probably by converting some or all to assembly language ) aggresively . The optimization can be by tweaking the algorithms , changing data types or structures used or converting some/all portion to assembly language. There are Interupt service routines handling communication with ADCs over SPI . We are an India based company dealing in power and energy measuring products . Established in 1993 . I am the technical director responsible for development of new ...
We need a PCB Layout Designer who can create a PCIE FPGA Board for us. The board should have the following features : XC7A35T Xilinx 7 Series FPGA FT601 FTDI USB 3.0 JTAG Module PCIe Gen2 or PCIe Gen1 See PDF for further information.
I want a personal statement for applying for a cybersecurity master's degree, from a fairly different base degree (electronics and communication bachelor ) but with some courses that relate to computer science, such as mobile application development, network engineering, embedded systems, computer programming, also my senior design project was related to cryptography on FPGA " Real-Time Encryption using FPGA " , finally i have security+ certification wich help in this matter .
Looking to engage with an advanced C developer that is familiar and productive in these areas... I expect this will be around six weeks of work to reach v0.1 EMBEDDED LINUX, custom hardware Key points in no particular order... Willing to be flexible during discovery phase! Raspberry Pi - specifically ZERO W Added hardware I/O elements C/C++ coding, not Java or Python Real-time operation SPI & I2C on multiple devices Non-blocking asynchronous code methods Familiarity with State Machines Cellular voice, SMS and data comms (SIM7600 modem) On board Wi-Fi (AP and client modes) ssh, http & serial configuration option Real time clock & timer events High availability design / WDT etc Multiple concurrent timers Serial Command / Menu parsing —————&...
registration of images using cross correlation between 2 overlapped images on fpga the requirements are finding the cross correlation results(coefficients) and should be normalized numbers. the code should be written in fpga verilog language. he must knows the algorithm of correlation, how to load images to fpga ,how to show and calculate is the 2nd time i post it. i have a nexys 4 ddr board or nexys artix_7 i am using vivado 2019.1 the period is 1-2 months the price depends on effort of work.
>Registrati o accedi per visualizzare i dettagli.
Looking for efficient Migration of Verilog Testbenches to UVM environments with Building constrained random test benches
Hi Duc D., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson
Hi Khanh L., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson
Hi Kevin N., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson
Hi Tiep N., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson
Hi Lic T., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson
Hi Quang T., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson
Huy, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson
