Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Assumi Verilog / VHDL Designers

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    41 lavori trovati, prezzi in EUR
    VHDL/Verilog Display Corrections 6 giorni left
    VERIFICATO

    Super easy project. I just need to change the HEX display for a seven segment decoder. I will send you a zip file with all of the information. Please message me for details.

    €23 (Avg Bid)
    €23 Offerta media
    6 offerte
    MIPS instructions Expert 6 giorni left
    VERIFICATO

    MIPS instructions Expert Only expert

    €6 - €19
    Sigillato
    €6 - €19
    1 offerte

    Implement your design using Magic VLSI layout tool to generate your project layout Test your design using irsim to simulate your project. Reqired Magic VLSI tool is running on ubuntu OS SRAM PROJECT VLSI

    €91 (Avg Bid)
    €91 Offerta media
    3 offerte

    I want to read and write 180 values in B-RAM , VIVADO using VHDL coding ,Will provide reference code

    €15 (Avg Bid)
    €15 Offerta media
    1 offerte

    I need help with my project. You must be good at RISC-V and Verilog. The project is related to Cache. Please check the file

    €27 (Avg Bid)
    €27 Offerta media
    1 offerte

    i need help in Implement MIPS processor pipeline and instruction and data caches, using VHDL. i will provide more details in the chat.

    €44 - €45
    €44 - €45
    0 offerte

    hi everyone, I need a fractal image compression code (for a 128*128 image) implemented on a DE2 cyclone II in the M4K memory which has 105 blocks.

    €126 (Avg Bid)
    €126 Offerta media
    3 offerte

    Design an 8-bit Addressable Latch with built in 1 of 8 Decode. The circuit is composed of three stages, the decoder, latch system and a buffer output.

    €131 (Avg Bid)
    €131 Offerta media
    6 offerte
    Verilog code simulation 5 giorni left
    VERIFICATO

    I have a project about ALU, logic unit with muxes

    €25 (Avg Bid)
    €25 Offerta media
    7 offerte
    Logic design 5 giorni left

    obtain the minimal expression from the given truth table and design the logic circuit from the simplified expression

    €11 (Avg Bid)
    €11 Offerta media
    16 offerte

    need to connect IR thermometer sensor to display

    €116 (Avg Bid)
    €116 Offerta media
    22 offerte

    project consists in a virtual analog music synthesizer running on Myr z-turn board, i need a developer for finishing this project and future ones.

    €30 / hr (Avg Bid)
    €30 / hr Offerta media
    8 offerte
    Matlab Expert required 4 giorni left
    VERIFICATO

    More details will be shared via chat

    €14 (Avg Bid)
    €14 Offerta media
    10 offerte
    Verilog/VHDL 4 giorni left
    VERIFICATO

    I need a person who can do verilog

    €18 / hr (Avg Bid)
    €18 / hr Offerta media
    5 offerte

    Implement the video codec work flow which is simulated in the vivado on the Zync board

    €436 (Avg Bid)
    €436 Offerta media
    2 offerte
    SRAM vlsi design -- 2 3 giorni left
    VERIFICATO

    Implement an SRAM circuit that has a 32 bytes with its associated decoder and multiplexer. The SRAM memory must have the following properties: 1- Addresses are from 0x8000 to 0x801F. 2- You can read and write one byte at a time. 3- The are special output signals that are required. They are listed in the table below.

    €6 - €62
    Sigillato
    €6 - €62
    2 offerte
    SRAM vlsi design 3 giorni left
    VERIFICATO

    Implement an SRAM circuit that has a 32 bytes with its associated decoder and multiplexer. The SRAM memory must have the following properties: 1- Addresses are from 0x8000 to 0x801F. 2- You can read and write one byte at a time. 3- The are special output signals that are required. They are listed in the table below.

    €6 - €62
    Sigillato
    €6 - €62
    3 offerte
    FPGA4student 4 giorni left
    VERIFICATO

    This VHDL project is to design and implement noise filtering, metastabiliy and synchronization of given signals

    €225 (Avg Bid)
    €225 Offerta media
    4 offerte

    Implement an interpreter for the language which i created & the sample programs are all in the programming language which i have invented, and run with the interpreter

    €131 (Avg Bid)
    €131 Offerta media
    8 offerte
    Dc motor pwm , vhdl using fpga -- 4 4 giorni left
    VERIFICATO

    I want program code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite) and I hope all of these including in the report also simulation in one report

    €50 (Avg Bid)
    €50 Offerta media
    6 offerte
    vhdl encoder 4 giorni left
    VERIFICATO

    I am looking for a real-time A-law/U-law encoder written in VHDL for implementing in a Lattice XP2 FPGA. The input to the encoder will be 16 bit PCM16, the output will be 8 bit a-law/U-law. The PCM16input will comprise of 24 channels. The CODEC will have 1 16 bit input. The 2k channels will be fed into the codec sequentially in blocks of 32 16bit samples. The CODEC shall handle a total of 10 Megasamples/second in real time. Each block of 32 16bit PCM data will be accompanied with a 4 bit channel number 0-23. The 8 bit companded output should have an extra 4 bit output that will hold the channel address that corresponds to the PCM channels from which it was created. The target FGA is a Lattice XP2-8 but the code will be demonstrated in the Lattice XP5 eval board as attached.

    €1878 (Avg Bid)
    €1878 Offerta media
    2 offerte

    Making a Blinking LED Project using IC PCF7926ATT/C1AC07J : 1- Source code for this Blink Circuit 2- The IDE that used to making the Source code 3- The programmer Tools that using to Debug the Code 4- If there're Libraries For the Microcontroller PCF7926ATT/C1AC07J

    €191 (Avg Bid)
    €191 Offerta media
    6 offerte
    Quartus II / VHDL Coding 3 giorni left
    VERIFICATO

    I am looking for an expert to do coding in VHDL language and then do simulation in Quartus II. I will share work details in chat

    €130 (Avg Bid)
    €130 Offerta media
    3 offerte

    Port design from Max10 FPGA to Lattice LFE5U part

    €3302 (Avg Bid)
    NDA
    €3302 Offerta media
    6 offerte
    Simple FSM using verilog 3 giorni left
    VERIFICATO

    Implement a FSM to detect a sequence of “101”. (Ex: 10101: will be detected as two “101”; 101101: will be detected as two “101”) • The input sequence is set by using the 16 switches. • Reset and read sequence are enabled by the push buttons. • Output, status, and current sequence position are displayed on the 7-Segment[3:0].

    €28 (Avg Bid)
    €28 Offerta media
    6 offerte

    Hello, I need design video transivver use de2-115 FPGA use SystemVerilog, ethernet and usb camera Rettru Mini HD 1080P. Video must be encrypted aes-256. De2-115 need recive command over ethernet for start/stop with host verification.

    €663 - €1326
    €663 - €1326
    0 offerte
    Design an ALU Using Verilog 2 giorni left
    VERIFICATO

    Top cell : alu I/O: bit 15 is the most significant bit. INPUTS: A(15:0) , B(15:0) , alu_code(4:0) ; OUTPUTS: C(15:0) overflow TOP MODULE: 16-bit Adder Module PRIMARY SIGNALS: BUS inputs/outputs and additional signals BUS signals: bit 15 is the most significant bit. All bus signals are named with upper case letters INPUTS: A[15:0], B[15:0],CODE[2:0] OUTPUTS: C[15:0] The budget has limit of $80 More details in Chat!

    €78 (Avg Bid)
    €78 Offerta media
    18 offerte

    I would like a FPGA miner for Equihash 125,4

    €1071 (Avg Bid)
    €1071 Offerta media
    4 offerte

    looking support for the verilog program and MIPS urgently . this tasks to be tested in vivado software . here i am attaching the detailed information for the tasks to be done and the supporting binaries which requires for the codes

    €57 (Avg Bid)
    €57 Offerta media
    3 offerte

    I want a code for 12/24 hr clock implementation in VHDLon basys 3 board

    €24 (Avg Bid)
    €24 Offerta media
    5 offerte
    Proyecto de circuito en Logisim 1 giorno left
    VERIFICATO

    Proyecto de circuito en Logisim

    €73 (Avg Bid)
    €73 Offerta media
    8 offerte

    I have some tasks related to computer architecture. I want someone who is an expert in VHDL.

    €9 / hr (Avg Bid)
    €9 / hr Offerta media
    2 offerte
    Program two microcontrollers -- 2 1 giorno left
    VERIFICATO

    Program microcontrollers and provide code for cloning and or copy process etc.

    €904 (Avg Bid)
    €904 Offerta media
    13 offerte

    Hi Looking for person who can support work from office or concern that can contract people to work for projects ( test bench development/ requirements writing / development and implementation tests/ simulation/ function coverage ) UVM / SYSTEM VERILOG must.

    €8 / hr (Avg Bid)
    €8 / hr Offerta media
    4 offerte
    MIPS programming expert needed 20 ore left
    VERIFICATO

    MIPS programming expert needed

    €16 (Avg Bid)
    €16 Offerta media
    2 offerte

    I have a project on mips and LEGv8 and need help

    €24 (Avg Bid)
    €24 Offerta media
    2 offerte

    The EE 272 Simple Neural Evaluation engine takes weights for a neural network, and applies them to input data. The design is flexible, and assumes very little about the neural network. This design assumes all data is contiguous and all weights are processed. The design assumes the input data is 24 bits per sample in 2’s complement form. For math reasons, the input number are commonly scaled to be between -1 and +1. This implies the data is actually 8.24 binary fixed point. This scaling is important when processing weights. The weights are assumed to be in 8.24 form. (32 bits fixed binary point) The neural network can have up to 4096 inputs per layer, and this adds 12 additional bits to the sum. There can be up to 4096 nodes per layer. The input data is mapped to 8.24 before operation...

    €156 (Avg Bid)
    €156 Offerta media
    3 offerte

    The EE 272 Simple Neural Evaluation engine takes weights for a neural network, and applies them to input data. The design is flexible and assumes very little about the neural network. This design assumes all data is contiguous and all weights are processed. The design assumes the input data is 24 bits per sample in 2’s complement form. For math reasons, the input number are commonly scaled to be between -1 and +1. This implies the data is actually 8.24 binary fixed point. This scaling is important when processing weights. The weights are assumed to be in 8.24 form. (32 bits fixed binary point) The neural network can have up to 4096 inputs per layer, and this adds 12 additional bits to the sum. There can be up to 4096 nodes per layer. The input data is mapped to 8.24 before operation...

    €27 (Avg Bid)
    €27 Offerta media
    1 offerte

    Need someone who is experts in MIPS

    €18 (Avg Bid)
    €18 Offerta media
    1 offerte
    verilog coding using ModelSim 2 ore left
    VERIFICATO

    looking for some help with my verilog coding project using ModelSim. please bid if you can

    €31 - €41
    Sigillato
    €31 - €41
    7 offerte