Verilog / VHDL Lavori e Concorsi
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.Sfoglia i Lavori su Freelancer
Progetto/Concorso | Descrizione | Offerte/Proposte | Competenze | Iniziato | Termina | Prezzo (EUR) | |
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DDR3 memory controller interface using nexys video board | We are working on nexys video board and we are trying to access DDR3 memory using IPCORE in vivado design suite software. We want to read and write data into DDR3 memory using nexys video board. | 1 | Programmazione C, Elettronica, Verilog / VHDL, Microcontrollore, Software integrato | Feb 21, 2018 | Oggi6d 23h | €13 | |
DDR3 Memory controller interface using nexys video board | We are working on nexys video board .We are trying to access DDR3 memory using IP core in Vivado design suit [url rimosso, accedi per visualizzarlo] want to read and write the data into DDR3 memory and access it in nexys video board. | 5 | Programmazione C, Elettronica, Verilog / VHDL, Microcontrollore, Arduino | Feb 19, 2018 | Feb 19, 20184d 22h | €289 | |
Verilog Servo controller | I'm looking for someone who can write me a verilog HDL code for a servo controller | 7 | Programmazione C, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA | Feb 18, 2018 | Feb 18, 20184d 15h | €23 | |
AI Based Chip Design For video codec h.264 for face recognition in cloud and verify output on Xilinx FPGA Kit | write an AI Algorithm for video codec h.264 and design Chip, after design chip of AI Based video codec h.264 you can verify out put on Xilinx FPGA Kit for face recognition in cloud iam expecting this project to finish on or before 26th feb2018 regards D RAMANNA [Removed by Freelancer.com Admin for offsiting - please see Section 13 of our Terms and Conditions] BANGALORE-INDIA | 2 | Graphic Design, Progettazione Loghi, Elettronica, Verilog / VHDL, Ingegneria Elettrica | Feb 18, 2018 | Feb 18, 20184d 9h | €170 | |
Enlarge a Circuit Design | I want to make a timing light like those that are used to set the ignition timing on an engine with a spark plug. I need to be able to delay the flash of the light from zero degrees to 720 degrees so that I can video what is happening to mechanisms on an engine while they are running without using a high speed camera. The engine will be running up to 8,000 RPM. I have found an example of ... | 16 | Ingegneria, Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica | Feb 17, 2018 | Feb 17, 20183d 18h | €155 | |
need help with mplab project | please give me full code for this project. using MPLAB software and production must be successful. make the PCB design. | 5 | Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, Configurazione Circuiti Stampati | Feb 17, 2018 | Feb 17, 20183d 11h | €29 | |
Electronic Engineer | We require an electronic engineer who is skilled in: FPGA Programming (VHDL) PicoBlaze embedded processor (Assembler) DWIN Technology TouchScreen | 7 | Programmazione C, Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica | Feb 16, 2018 | Feb 16, 20182d 16h | €25 | |
FPGA Based NMR Spectrometer design | Need to design a FPGA based NMR Spectrometer for NMR Applications. Phase 1 : Interface high speed ADC and DAC with Altera FPGA and write the software for generating RF pulses and Capture Echo Signal from ADC. See the attached similar work for more details. | 10 | Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA | Feb 16, 2018 | Feb 16, 20182d 8h | €6440 | |
Design an analog to digital convereter | Aim is to design a successive approximation register based analog to digital converter using cadence tool (any vlsi back end tool) | 10 | Ingegneria, Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica | Feb 16, 2018 | Feb 16, 20182d 1h | €813 | |
adc ltc2308 in vhdl altera deo nano soc cyclone 5 board | It is a basic project but since I've never worked with on FPGA before, I think someone with experience is a wise choice. The project is basically read the ADC signal from onboard adc ltc2308 and send it to the DAC. While ADC (ltc2308 ) is 12bit | 7 | Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, Progettazione di Circuiti | Feb 12, 2018 | Feb 12, 2018Terminato | €66 | |
need someone for FPGA work | I would like someone to help me build a simple FPGA Kernel for a certain gaming system. I would like your help to improve a FPGA project we are using Altera Quartus programming software i have attached a QAR file First of all, compile it to a POF file and then send it to me and let me examine it and I will give you more instructions on how to proceed. It's not very complicated Let me ask... | 9 | Programmazione C, Elettronica, Verilog / VHDL, Microcontrollore, FPGA | Feb 12, 2018 | Feb 12, 2018Terminato | €125 | |
An expert in FPGA is required | I would like someone to help me build a simple FPGA Kernel for a certain gaming system. | 4 | Programmazione C, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA | Feb 12, 2018 | Feb 12, 2018Terminato | €121 | |
FPGA QAR Project | I have a QAR file that I cannot compile into a POF or PLD file, I would like someone with experience in FPGA to do it. It must be someone with real good knowledge of FPGA. | 14 | Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA | Feb 12, 2018 | Feb 12, 2018Terminato | €399 | |
Help with plptools needed need perfect work | Help with plptools needed need perfect work.. All the details would be given on the chat... Need to submit it till midnight today... | 2 | Matlab and Mathematica, Verilog / VHDL, Microcontrollore, Matematica, , Assembly | Feb 11, 2018 | Feb 11, 201810h 5m | €61 | |
FPGA work .... | I would like someone to help me build a simple FPGA Kernel for a certain gaming system. | 5 | Programmazione C, Elettronica, Verilog / VHDL, Microcontrollore, FPGA | Feb 11, 2018 | Feb 11, 2018Terminato | €22 | |
FPGA CONSOLE | I would like someone to help me build a simple FPGA Kernel for a certain gaming system. | 5 | Programmazione C, Elettronica, Verilog / VHDL, Microcontrollore, FPGA | Feb 11, 2018 | Feb 11, 2018Terminato | €17 | |
OFDM/256QAM Modulation/Demodulation and Forward Error Correction in Matlab/Xilinx FPGA IP | We are looking for develop and implement OFDM / 16QAM, 32QAM, 64QAM , 256QAM Modulation / Demodulation algorithm with Matlab and implement it on Xilinx Zynq FPGA . 1- BW : tunable upto 40Mhz . 2- FEC : LDPC or Reed solomon . | 11 | Ingegneria, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, LabVIEW | Feb 9, 2018 | Feb 9, 2018Terminato | €2133 | |
Use edaplayground to run a carry lookahead adder | need a 4-bit carry look ahead adder to be coded in system Verilog using edaplayground. 1) write system Verilog model for CLA 2) parameterize for N bits 3) generate/write test bench that works | 11 | Programmazione C, Verilog / VHDL, Microcontrollore, Architettura Software, FPGA | Feb 8, 2018 | Feb 8, 2018Terminato | €19 | |
Controller (Microprocessor Based) Design for Transport Refrigeration System | Design , Prototyping of Controller (Microprocessor Based) Design for Transport Refrigeration System to control a system powered by diesel engine based power train and comprising of a Vapour Compression Cycle Refrigeration System comprising of Refrigeration Compressors , Condensors ,Evaporators , heaters etc | 7 | Elettronica, Verilog / VHDL, Ingegneria Elettrica, Configurazione Circuiti Stampati, Progettazione di Circuiti | Feb 8, 2018 | Feb 8, 2018Terminato | €545 | |
Steganography - open to bidding | I need a C# based Desktop Applications With Following Modules The Encryption Module 1. Registration: - To access the core system, user first need to register themselves by providing required details. 2. Login: - After registration, user may login into the system. 3. Algorithm Selection: - Here, user will select the algorithm such as DES (Data Encryption Standard), AES (Advance Encryption Standa... | 7 | Matlab and Mathematica, Verilog / VHDL, Algoritmo, Configurazione Circuiti Stampati, Apprendimento Automatico | Feb 7, 2018 | Feb 7, 2018Terminato | €217 | |
CONFIGURATION OF ADS 5263 EVM WITH ZC702 OR KC705. | i have ADS5263 EVM board, and i connected that board with xilinx zc702 via ADC FMC adapter. i tried to write code for that i failed to generate bit stream based on xilinx application note xapp524. i need help to sort out the problem of clock multi region routing. | 5 | Verilog / VHDL | Feb 6, 2018 | Feb 6, 2018Terminato | €122 | |
integration wsn with clouds using cooja | i want a specialist in cloud integration with wsn and have experience in cooja. | 9 | Java, Ingegneria, Matlab and Mathematica, Verilog / VHDL, Programmazione C++ | Feb 6, 2018 | Feb 6, 2018Terminato | €83 | |
FIR Filter Reference Design in Verilog | We are looking for a FIR filter design in Verilog with the following requirements: - 16-bit input, 16-bit fixed coefficient - 39-bit output - 256 taps Please provide 2 implementations: 1. serial implementation using 1 multiplier 2. partial parallel implementation with 4 multiplers | 5 | Verilog / VHDL, FPGA | Feb 4, 2018 | Feb 4, 2018Terminato | €178 | |
Simple MIPS interpretor | Want someone to finish a MIPS project. The project will be required to be finished by the end of the day | 8 | Programmazione C, Verilog / VHDL, Architettura Software, Assembly, Assemblatore x86/x64 | Feb 4, 2018 | Feb 4, 2018Terminato | €42 | |
Recursive karatsuba multiplier (16bit) | I need a verilog code for recursive karatsuba multiplier for 16bit signed integers. | 6 | Verilog / VHDL, Design Digitale | Feb 2, 2018 | Feb 2, 2018Terminato | €158 | |
Pthread and OpenMP | I have some simple code that I want to compare in OpenMP and pThread to see which is more performant. | 1 | Programmazione C, Java, Verilog / VHDL, Programmazione C++, Assembly | Jan 31, 2018 | Jan 31, 2018Terminato | €28 | |
dead reckoning Indoor positioning system | we want to develop an indoor positioning system using pedestrian dead reckoning method. we are using STM32F469NI microcontroller. using only accelerometer and gyroscope. we have successfully collected the data for accelerometer and gyroscope. so is it possible to employ these data in embedded platform (keil u-vission) to develop the system. other possibility is to save the data in SD card and use ... | 15 | Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, LabVIEW, Arduino | Jan 30, 2018 | Jan 30, 2018Terminato | €160 | |
Petalinux on ZC706 | I am looking for someone who has done work on Petalinux on ZC706 or Zedboard. The person MUST have done projects of Ethernet, PS Ram usage, external permanent memory storage using PCIe based drive, SPI control. I need to develop a project using above features. | 1 | Verilog / VHDL, FPGA | Jan 29, 2018 | Jan 29, 2018Terminato | €135 | |
ddr sdram controller | i want to do some modification to controller i.e either adding a module to it or pipeling it. | 3 | Verilog / VHDL | Jan 20, 2018 | OggiTerminato | €182 | |
build a mips recursive quicksort | use recursive way to write quicksort in mips, the c code will be offered | 9 | Programmazione C, Verilog / VHDL, Programmazione C++, Assembly, Assemblatore x86/x64 | Jan 17, 2018 | Jan 17, 2018Terminato | €33 | |
Matlab Simulation-Impulse Voltage generation | Need to modify a schematic(.mdl) to get desired results. The .mdl schematic is attached [url rimosso, accedi per visualizzarlo] need to modify the design to get proper output like Figure 4 | 12 | Ingegneria, Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica | Jan 10, 2018 | Jan 10, 2018Terminato | €34 | |
need a VHDL expert asap | vhdl expert needed asap to run a code | 16 | Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, FPGA | Jan 10, 2018 | Jan 10, 2018Terminato | €16 | |
License Plate Detection Using VHDL | I'm building a license plate detection system, and concept has been proven using MATLAB. The current challenge is to implement the design on an Altera DE Board FPGA using VHDL. At this point, because of time constraints I like to ask for ur assistance in the following areas I seek someone who could help Implement the design on an FPGA. Attached is the matlab code | 8 | Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, FPGA | Jan 9, 2018 | Jan 9, 2018Terminato | €463 | |
Edge detection on Altera DE2-115 | Hello, i want to create project using altera DE2-115 board to detect edges on 3 image using sobel filter and show they ober VGA 640x480. To choose which image should be apear is needed 2 swtich. i have done some algorithm with matlab and now i have to implement it on altera. Thanks | 16 | Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, LabVIEW | Jan 6, 2018 | Jan 6, 2018Terminato | €522 | |
This task need to be developed using MATLAB....A cicuit bsed on fuzzy logic to detect different kind of faults L-G,L-L,LLL etc. | Fuzzy logic based fault detection | 9 | Ingegneria, Matlab and Mathematica, Verilog / VHDL, Algoritmo, Ingegneria Elettrica | Jan 6, 2018 | Jan 6, 2018Terminato | €28 | |
SFP communication with FPGA | Coding required for FPGA to SFP communication | 13 | Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA | Jan 6, 2018 | Jan 6, 2018Terminato | €727 | |
VHDL for programming FPGA board | Hi, I run a small sales business in the video game industry. I am looking for someone with VHDL experience to assign pins on an FPGA board for an old video game system, to a new pre-designed break out board to allow the system to use HDMI. Please contact for details. | 18 | Verilog / VHDL, FPGA | Jan 2, 2018 | Jan 2, 2018Terminato | €103 | |
FPGA Design in VHDL | Design of FPGA to serve as a memory mapped resource for a local processor module. The processor interface is a memory mapped address/data bus. The FPGA design contains registers, counters and data path functions. System clock frequency is 25MHz. No internal processor is used within the FPGA. An external SRAM is required for expanded data storage. The target FPGA is the Microsemi ProASIC3E. | 10 | Verilog / VHDL, Design | Jan 2, 2018 | Jan 2, 2018Terminato | €5543 | |
Project for Varun V. | Hi Varun V., I noticed your profile and would like to offer you my project. We can discuss any details over chat. | 1 | Programmazione C, Linux, Verilog / VHDL, Software integrato, | Jan 1, 2018 | Jan 1, 2018Terminato | €203 | |
Work with Digital Electronic and Analogue... | Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. | 11 | Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica | Dec 28, 2017 | Dec 28, 2017Terminato | €21 | |
Work with Digital Electronic and Analogue. | Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. | 11 | Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica | Dec 28, 2017 | Dec 28, 2017Terminato | €28 | |
Work with Digital Electronic and Analogue | Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. | 13 | Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, FPGA | Dec 28, 2017 | Dec 28, 2017Terminato | €27 | |
Work with Digital Electronic and Analogue | Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. | 13 | Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica | Dec 27, 2017 | Dec 27, 2017Terminato | €37 | |
Convert some VHDL to Verilog | Contact me for more details. All I need done is porting some VHDL to Verilog. | 18 | Ingegneria, Verilog / VHDL, Microcontrollore, Architettura Software, FPGA | Dec 23, 2017 | Dec 23, 2017Terminato | €96 | |
ASIC Design-Verification article on UVM | Dear ASIC Verification Experts, I am looking for ghost writer who is from ASIC verification background. I want a unique article which tries to explain why we need to use UVM (Universal Verification Methodology). The title of the article will be similar as this. "If SystemVerilog is so good, why do we need the UVM? ". The article needs to start by answering this question in title. The... | 3 | Verilog / VHDL | Dec 23, 2017 | Dec 23, 2017Terminato | €81 | |
vhdl code using altera | Design a digital system that will generate police or unbalance siren sound | 9 | Ingegneria, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA | Dec 22, 2017 | Dec 22, 2017Terminato | €106 | |
Designing Pipelined RISC 32-bit processor by Logisim simulator - 22/12/2017 12:13 EST | Objectives : Using the Logisim simulator Designing and testing a RISC 32-bit processor Instruction Set Architecture In this project, you will design a simple 32-bit RISC processor with sixteen 32-bit general purpose registers: R0 through R15. R0 is hardwired to zero and cannot be written, so we are left with fifteen registers. There is also one special-purpose 24-bit program counter (PC)... | 7 | Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, Progettazione di Circuiti | Dec 22, 2017 | Dec 22, 2017Terminato | €111 | |
FPGA Project (VHDL floating and real number mathematical operations using Simulink MATLAB) | I need a vhdl program allowing FPGA to do aritmetic calculations with real values. For instance summing, substracting, dividing and multiplying 2 real number values as follows: (2.32 + 3.65; 2.32 - 3.65; 2.32/3.65 ; 2.32*3.65) I assume it suppose to be done using some toolbox on MATLAB ( System Generator Toolbox) This code should work on Xilinx Spartan 6. I want the code written simp... | 10 | Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, LabVIEW, FPGA | Dec 21, 2017 | Dec 21, 2017Terminato | €53 | |
Vhdl and test bench for flip flop | I need to build a t flip flop in vhdl and write a test bench for it which shows simulation results then using t flip flop implement 4 bit ripple binary counter in a structural method in vhdl and write a test bench and show simulation results it's a report in PDF | 8 | Verilog / VHDL | Dec 20, 2017 | Dec 20, 2017Terminato | €55 | |
Parking meter | The project is to design and implement a parking meter. o When you add a coin to the parking meter, time is added during which you can legally park your car. The meter shows the remaining time in a unit of second continuously, and stops at zero. Types of coins and their worth Pushbutton 0 (PB0) Add 30 seconds Pushbutton 1 (PB1) Add 60 seconds Pushbutton 2 (PB2) Add 120 seconds Pushbutto... | 7 | Verilog / VHDL | Dec 19, 2017 | Dec 19, 2017Terminato | €18 |
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