Verilog / VHDL Lavori e Concorsi

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
Registrati e inizia a guadagnare
Registrati per iniziare a guadagnare. Sei un a Verilog / VHDL Designer? Potresti guadagnare eseguendo questi lavori!

Sfoglia i Lavori su Freelancer

Progetto/Concorso Descrizione Offerte/Proposte Competenze Iniziato Termina Prezzo (EUR)
Digital system and microprocessor small task small task on digital system and microprocessor using verilog amount usd 20 time 1 day 7 Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA Oct 21, 2017 Oggi6d 16h €20
Custom Verilog design We need to build a custom Verilog design. Please message for further details. 8 Ingegneria, Verilog / VHDL, Ingegneria Elettrica, LabVIEW, FPGA Oct 21, 2017 Oggi6d 12h €20
project verilog Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 9 Programmazione C, Ingegneria, Verilog / VHDL, Ingegneria Elettrica, FPGA Oct 21, 2017 Oggi6d 2h €10
VLSI design and testability using SPICE/ Verilog/VHDL An applied project may involve using tools such as Spice, Verilog/VHDL, etc. to demonstrate its success 9 Verilog / VHDL, Very-large-scale integration (VLSI) Oct 20, 2017 Oct 20, 20175d 17h €377
Logisim Software Tasks Hi I need someone who is good with Logisim Software to complete some tasks. 9 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica Oct 20, 2017 Oct 20, 20175d 12h €22
Power Generation Simulation using LabVIEW Power Generation Simulation using LabVIEW. Power generation stations will often consist of a number of individual generators where each generates a proportion of the overall station’s output. Need two separate applications. Application 1 and Application 2. 8 Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, LabVIEW, Arduino Oct 20, 2017 Oct 20, 20175d 3h €46
Digital design using Verilog Use Basys 3 Board and Vivado 2016.2 I'll share the rest details 7 Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, LabVIEW, FPGA Oct 20, 2017 Oct 20, 20175d 3h €36
VHDL Radio Clock + python script Need help in VHDL everything is mentioned on the PDF 7 Elettronica, Verilog / VHDL, Testare Software, Ingegneria Elettrica, FPGA Oct 19, 2017 Oct 19, 20174d 6h €60
Project for Gabriel G. I need help with capsim practice rounds 4 Gestione Progetti, Telemarketing, Excel, Matlab and Mathematica, Verilog / VHDL Oct 18, 2017 Oct 18, 20173d 19h €21
verilog project making verilog on quartus II (cyclone IV) 11 Ingegneria, Verilog / VHDL, Architettura Software, Assembly, FPGA Oct 18, 2017 Oct 18, 20173d 13h €123
Cloudsim project I want someone to work on programming part in cloudsim that includes migration, Placement, scheduling and power consumption. 2 Programmazione C, Java, Verilog / VHDL, Architettura Software, Programmazione C++ Oct 18, 2017 Oct 18, 20173d 2h €52
Verilog programming - 18/10/2017 00:34 EDT Simple verilog programming project. Create an ALU with full [url rimosso, accedi per visualizzarlo] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. 13 Verilog / VHDL Oct 18, 2017 Oct 18, 20173d 1h €81
Verification Of Motion Estimator Using UVM Verification Of Motion Estimator Using UVM(Universal Verification Methodology) 5 Verilog / VHDL, Ingegneria Elettrica, Very-large-scale integration (VLSI) Oct 17, 2017 Oct 17, 20173d €202
Verilog programming Simple verilog programming project. Create an ALU with full [url rimosso, accedi per visualizzarlo] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. 5 Verilog / VHDL Oct 17, 2017 Oct 17, 20172d 21h €76
ASIC Design in Verilog This project is related to Computational Neural Networks 2 Matlab and Mathematica, Verilog / VHDL, Neural Networks Oct 17, 2017 Oct 17, 20172d 17h €130
VHDL Radio clock everything is going to be explained on the pdf 11 Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA Oct 17, 2017 Oct 17, 20172d 16h €34
Design of audio visualiser using DE2-115 Altera board I want to implement an audio visualizer on the screen of the voice spoken through the mic or played using SD card. 4 Verilog / VHDL Oct 17, 2017 Oct 17, 20172d 13h €198
Matlab power system Simulation using Simulink -- 2 - 17/10/2017 07:15 EDT My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa 13 Ingegneria, Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica Oct 17, 2017 Oct 17, 20172d 8h €116
Matlab power system Simulation using Simulink My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa 10 Ingegneria, Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica Oct 17, 2017 Oct 17, 20172d 6h €133
Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, LabVIEW Oct 16, 2017 Oct 16, 20172d
netlist construction in EE using C++ refactor the sample code by using the c++ 9 Programmazione C, Verilog / VHDL, Programmazione C#, Ingegneria Elettrica, Programmazione C++ Oct 16, 2017 Oct 16, 20171d 13h €115
project for Ahmed M -- 2 - 16/10/2017 12:09 EDT I believe you must do this project. 2 Verilog / VHDL Oct 16, 2017 Oct 16, 20171d 13h €108
project for Ahmed M I believe you must do this project. 2 Verilog / VHDL Oct 16, 2017 Oct 16, 20171d 13h €132
verilog project want verilog code on fpga i want soon 2 Ingegneria, Verilog / VHDL, Architettura Software, LabVIEW, FPGA Oct 16, 2017 Oct 16, 20171d 12h €7
ASIC Designs and Development Hello. I am into a project that involves creating PCB / ASIC design with FPGA/CLPD. The specified ASIC Architecture as a product needs to be able calculate one or more algorithms connected through some type of data socket. Performance and power is important. I am interrested to get in touch with a board designer and vhdl developer that have knowledge both with electrical layouts and vhdl. ... 6 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, Configurazione Circuiti Stampati Oct 16, 2017 Oct 16, 20171d 5h €13
veriloghdl code for calculation area THis must implement on quartus( altera FPGA cyclone IV) 4 Programmazione C, Verilog / VHDL, Microcontrollore, Programmazione C++, FPGA Oct 16, 2017 Oct 16, 20171d 5h €87
making verlog hdl code calculataion area in black and white image on fpga ( cyclone IV) 8 Programmazione C, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, Programmazione C++ Oct 16, 2017 Oct 16, 20171d 1h €106
VHDL Coursework help in VHDL codes ,, everything will be explained later 13 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica Oct 15, 2017 Oct 15, 201717h 11m €47
fpga software I want to read programmes in FPGA chips 17 Programmazione C, Verilog / VHDL, Architettura Software, FPGA Oct 15, 2017 Oct 15, 201711h 33m €350
creation of hardware module using verilog which will be able to communicate with the memory of the processor using Verilog which will be able to communicate with the memory of the processor 4 Verilog / VHDL Oct 14, 2017 Oct 14, 2017Terminato €53
simple verilog hdl code calculate each area in black and white image 11 Programmazione C, Ingegneria, Verilog / VHDL, Microcontrollore, FPGA Oct 13, 2017 Oct 13, 2017Terminato €40
Simple Verilog Project Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3. 8 Ingegneria, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, FPGA Oct 13, 2017 Oct 13, 2017Terminato €20
Color space conversions and FPGA's 3 pages report in two parts on: (i) fundamental information about FPGAs and their programming, and (ii) standard color spaces and formulas for converting those color spaces into other ones. (Plagarism free) finished in 3 days maximum. 9 Ingegneria, Verilog / VHDL, Ingegneria Elettrica, FPGA Oct 13, 2017 Oct 13, 2017Terminato €56
Build software Looking for expert in FPGA and verilog 18 Programmazione C, Verilog / VHDL, Architettura Software, Programmazione C++, FPGA Oct 12, 2017 Oct 12, 2017Terminato €407
Statcom in simulink Power electronics expert -- 2 Statcom in simulink Power electronics expert needed 9 Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, FPGA Oct 11, 2017 Oct 11, 2017Terminato €139
Want to develop robotic program and test the same with simulation to check feasibility of and automation idea Existing : Manual labours are lifting filled 25 kg bags from stack of machine palletised load (40 bags per wooden pallet, and loading into trucks, containers. Automation solution : Using three axis gantry robot, vacuum lifting end tool and smart programming to create fully automatic truck loading system. All above only on simulation, 3d models to check feasibility of solutions and then to us... 5 Matlab and Mathematica, Verilog / VHDL, Architettura Software, Progettazione Software, Programmazione Oct 11, 2017 Oct 11, 2017Terminato €3971
VLSI PROJECTS FIND THE ATTACHED IEEE [url rimosso, accedi per visualizzarlo] REQUIREMENTS 4 Verilog / VHDL, FPGA, Very-large-scale integration (VLSI) Oct 11, 2017 Oct 11, 2017Terminato €73
Statcom in simulink Power electronics expert Statcom in simulink Power electronics expert needed 9 Elettronica, Matlab and Mathematica, Verilog / VHDL, FPGA Oct 11, 2017 Oct 11, 2017Terminato €96
Convert a code from Aptech Gauss language into Matlab with Parallel processing. I have a code written in Aptech Gauss program that I want to convert into Matlab and I want the code to run under CUDA power in Matlab. 3 Matlab and Mathematica, Verilog / VHDL, Architettura Software, CUDA, Progettazione Software Oct 10, 2017 Oct 10, 2017Terminato €130
Prelab Write VHDL code 7 Verilog / VHDL Oct 10, 2017 Oct 10, 2017Terminato €23
dimensionality reduction using PCA we will consider use of PCA for simple dimensionality reduction, i.e., determining the signal subspace when there are more observations than the underlying latent variables—signals. The main assumption here is that both the noise and signals are independent and identically distributed Gaussians, however the the signals are correlated among themselves while the noise components are not, ... 14 Matlab and Mathematica, Verilog / VHDL, Analisi agli Elementi Finiti , CUDA, FPGA Oct 10, 2017 Oct 10, 2017Terminato €346
Altera DE115 - Audio signal processing Record voice , Add and Remove Noise and play back recording. Design and implement the verilog code on an Altera DE2-115 Development Board. Available Hardware Microphones, Speakers 9 Verilog / VHDL, Microcontrollore, Software integrato, Assembly, FPGA Oct 10, 2017 Oct 10, 2017Terminato €192
Audio Signal Processing AIM - Record Audio , Add and Remove Noise and play back audio. To design and implement the Embedded System centred on an Altera DE2-115 Development Board. The project should be based on a Verilog HDL implementation. Available Hardware In addition to the DE2-115 board, the following hardware devices are available. If you wish to do a project requiring hardware support but don’t see the... 7 Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, Software integrato, FPGA Oct 10, 2017 Oct 10, 2017Terminato €432
Sequence Diagram There is a service class called PurchaseOrder that is called when a customer makes a purchase. It has a public method purchase(Account, Order). It does the following. a. Call [url rimosso, accedi per visualizzarlo]() b. Call [url rimosso, accedi per visualizzarlo](Account) c. Call [url rimosso, accedi per visualizzarlo]() d. [url rimosso, accedi per visualizzarlo]() calls [url rimosso, accedi ... 6 Verilog / VHDL, Architettura Software, PLC & SCADA, Analisi agli Elementi Finiti , Disegno per Ingegneria Oct 10, 2017 Oct 10, 2017Terminato €31
Matlab Program for Harmonics Analysis for a sampled data (Data in excel format) Need a Matlab program to perform Harmonics Analysis for a sampled data (data in Excel format). Matlab Codes must structured to read data from Excel file. Please find the attached Excel file [url rimosso, accedi per visualizzarlo] 22 Excel, Matlab and Mathematica, Verilog / VHDL, Architettura Software, Progettazione Software Oct 7, 2017 Oct 7, 2017Terminato €18
UML/MARTE modeling I want to build an interface(which consists of rules) to transform any MML model to a UML-MARTE model using AGG(algebraic graph transformation). 1 Verilog / VHDL, Progettazione UML, Analisi agli Elementi Finiti , SAS, CATIA Oct 7, 2017 Oct 7, 2017Terminato €498
matlab report making 10 pages minimum hi discussion via chat no front milestone need it in 12 hrs 10 mages maximum paper should be in IEEE formats no plagiarism is there.. please give a good quote 10 Matlab and Mathematica, Verilog / VHDL, LaTeX, Matematica, Fisica Oct 7, 2017 Oct 7, 2017Terminato €41
Matlab Write a Function for Forward Kinematics of the RPR Robot Input Format are the joint angles in radian, as shown in the figure is the extension of the prismatic joint in inches, as shown in the figure Output Format R is a 3x3 rotation matrix representing (Note: where represents a point in frame x) pos is a 4x3 matrix where each row contains the x,y,z coordinates represented as [x y z] in matrix form. Each row is the x,y,z coordinates of a point... 16 Matlab and Mathematica, Verilog / VHDL, Architettura Software, Analisi agli Elementi Finiti , Progettazione Software Oct 7, 2017 Oct 7, 2017Terminato €32
String compare algorithm need an algorithm that would compare two long strings delimited by | 3 Matlab and Mathematica, Verilog / VHDL, Algoritmo, CUDA, Apprendimento Automatico Oct 7, 2017 Oct 7, 2017Terminato €1663
Cryptoanalysis - Cryptograpgy - C programming I am looking for someone to write me a code in c that will test the cryptographic strength of the passwords. I can share more specific instructions and dummy passwords. I need a simple program. 9 Programmazione C, Verilog / VHDL, Architettura Software, Prolog, Programmazione C++ Oct 6, 2017 Oct 6, 2017Terminato €58
Showing 1 to 50 of 116 entries
« 1 2 3 »