Verilog / VHDL Lavori e Concorsi

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
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Progetto/Concorso Descrizione Offerte/Proposte Competenze Iniziato Termina Prezzo (EUR)
calculate speed between two points in verilog im making missile command and i have (x1,y1) and (x2,y2). how can I calculate the x step and y step values? 5 Verilog / VHDL Dec 12, 2017 Oggi6d 20h €33
Finite State machine for washing machine FPGA We need an expert of FPGA for fsm of washing machine analysis and synthesizes 5 Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA Dec 12, 2017 Oggi6d 18h €80
little project about emitter follower (manually and simulated) -- 2 - 11/12/2017 21:32 EST Help me to design the circuit attatched and find out the unkown parameters both 10 Ingegneria, Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica Dec 11, 2017 Oggi6d 14h €27
Analogue & Digital Electronic Please, see the attached file. Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. 16 Ingegneria, Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica Dec 11, 2017 Oggi6d 9h €176
multisim function generator hi i want someone to connect the function generator and the scope in multisim of electric circuit thank you 8 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, Progettazione di Circuiti Dec 11, 2017 Oggi6d 8h €20
Simulink to VHDL I have done a controller for a battery energy storage system using Matlab Simulink. I need to generate VHDL codes for my controller. If you have NOT done that, please do not wast my time. 5 Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, FPGA Dec 11, 2017 Oggi6d 3h €20
Microprocessor Project using CodeWarrior Software Hi, Need the completed project in 36 hours. Share the codes in 24 hours and the report in 36 hours. Project details are attached here. Sample codes are attached in the files. You need to use the similar codes for the work 4 Ingegneria, Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica Dec 11, 2017 Dec 11, 20175d 20h €85
VHDL to Verilog Translation I have .vhdl files for an implementation of google chrome's 'dino run' which appears when the user has no wifi connection. However, I would like to have the same functionality with Verilog description language. 8 Verilog / VHDL Dec 10, 2017 Dec 10, 20175d 14h €103
FPGA developer Looking for a developer to code a specific simple algorithm which is based around SHA3 (Keccak) into iCE40UltraPlus FPGA using the standard low-cost breakout board from Lattice: iCE40UP5K-B-EVN. In general there will be incoming data block over a serial channel, encrypting, and sending it back to the same serial channel. More details will be given in personal communication. I am not sure about ... 13 Elettronica, Verilog / VHDL, FPGA Dec 9, 2017 Dec 9, 20174d 3h €26
simulation/ VHDL Expert Needed -- Urgent job -- b I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 7 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, FPGA Dec 9, 2017 Dec 9, 20173d 19h €47
System verilog Verification Project Plz contact me. I have other code for it as well. You will just need to restructure the code and it should be good enough. 12 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, FPGA Dec 9, 2017 Dec 9, 20173d 19h €22
simulation/ VHDL Expert Needed -- Urgent job -- 3 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 2 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica Dec 9, 2017 Dec 9, 20173d 19h €36
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 2 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica Dec 9, 2017 Dec 9, 20173d 19h €30
simulation/ VHDL Expert Needed -- Urgent job -- 2 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 2 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica Dec 9, 2017 Dec 9, 20173d 19h €30
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 0 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, FPGA Dec 9, 2017 Dec 9, 20173d 19h -
simulation/ VHDL Expert Needed -- 2 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 4 Ingegneria, Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica Dec 9, 2017 Dec 9, 20173d 19h €29
simulation/ VHDL Expert Needed I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 7 Ingegneria, Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica Dec 9, 2017 Dec 9, 20173d 18h €33
Electronics Engineer/Tutor Hi, I am looking for a Electronics Engineer/Tutor who can tutor me some important concepts of the Engineering Design. I am looking for someone who has background in Electronics and Digital Logic Design. Happy Bidding! 20 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica Dec 8, 2017 Dec 8, 20173d 16h €10
DDR SD ram controller DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero 10 Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA Dec 8, 2017 Dec 8, 20172d 18h €373
FPGA Implementation of FIR filter 1. FIR design and simultion in Matlab. 2. Implement in FPGA(Xilinx Virtex-6 LX240T) and inter-connect with other logic blocks. 3. define registers for FIR filter and gain setting such that user can download filter co-efficients and gain settings through software to FPGA. 24 Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, FPGA Dec 7, 2017 Dec 7, 20172d 15h €665
Digital Logic Circuit using Logisim Hello, I am looking to build a circuit in Logisim that requires digital logic expertise. Project description will be provided upon contact. Computer science backgrounds, circuit design, and digital logic expertise required (preferably using Logisim). 22 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, Design Digitale Dec 6, 2017 Dec 6, 20171d 7h €73
need help with missile command game on de2-115 does anyone experienced with verilog have de2-115 I need help displaying a sprite on the screen. I have all the files. 4 Verilog / VHDL Dec 5, 2017 Dec 5, 20175h 54m €108
micro controller need somebody good in micro controller and has ever coded using vhdl 18 Programmazione C, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA Dec 5, 2017 Dec 5, 20173h 7m €148
Expert in Xilinx (VHDL-BASED) An efficient Glitch power reduction using sequential clock gating in VLSI circuits 8 Verilog / VHDL Dec 5, 2017 Dec 5, 2017Terminato €138
Project for SqUa11 -- 2 3x3 Systolic array matrix using rom and ram 2 Ingegneria, Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, Dec 4, 2017 Dec 4, 20172d 15h €10
Embedded systems Develop a minimal system that contains a PC, a microprocessor board, and an FPGA board. With this system, a PC application allows a user to “awaken” (or “start up”) the FPGA board through the microprocessor board. Once (and only after) the FPGA board is awakened, it waits for a push button action. After the button is pushed, it sends an 8-bit value in bit-serial to the... 9 Elettronica, Verilog / VHDL, Microcontrollore, Architettura Software, Arduino Dec 4, 2017 Dec 4, 2017Terminato €36
Implementation of 32-bit MIPS Processor I need someone who knows MIPS Assembly Language and knows how to use the LogicWorks software to design a Single-cycle processor (see Figure 1 in attached document) and a Five-stage pipelined processor (see Figure 2 in attached document). Please keep all bids within the budget, otherwise you will not be selected for the project. 7 Programmazione C, Verilog / VHDL, Architettura Software, Assembly, Assemblatore x86/x64 Dec 4, 2017 Dec 4, 2017Terminato €99
Write an article about UVM (universal verification methodology) Dear ASIC Verification Experts, I am looking for ghost writer who is from ASIC verification background. I want a unique article which tries to explain why we need to use UVM. The title of the article will be similar as this. "If SystemVerilog is so good, why do we need the UVM? " The article needed to be original and meaningful content. Please bid with your experience in ASIC ver... 26 Verilog / VHDL, Scrittura Tecnica Dec 4, 2017 Dec 4, 2017Terminato €83
putty language i need someone who can do putty and verilog 7 Ingegneria, Verilog / VHDL, Ingegneria Elettrica, Assembly Dec 4, 2017 Dec 4, 2017Terminato €94
Verilog Work I need some work done in verilog using Quartus 2 version 13 12 Verilog / VHDL Dec 3, 2017 Dec 3, 2017Terminato €123
putty coding language need an electrical engineer or computer engineer with background in putty language coding 3 Verilog / VHDL, Ingegneria Elettrica, Coding, Programmazione Dec 3, 2017 Dec 3, 2017Terminato €24
Need a Cadence design to design a amplifier circuit. Need a Cadence design to design a amplifier circuit. details will be share in chat box. 21 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, Progettazione di Circuiti Dec 3, 2017 Dec 3, 2017Terminato €21
Design of MIPS Datapath components Using Logisim Course: Computer Organization and Architecture Project: Design of MIPS Datapath components Using Logisim Objectives After completing this project you will: · Design a 32x 32 bit register file · Design a 32 bit arithmetic and logic unit (ALU) Register File The register file consists of 32 x 32-bit registers and has the following interface as shown in Figure 1: _ BusA and BusB... 10 Ingegneria, Elettronica, Verilog / VHDL, Progettazione di Circuiti, FPGA Dec 2, 2017 Dec 2, 2017Terminato €38
MATLAB code- a bit-serial CORDIC computer in Verilog MATLAB code a bit-serial CORDIC computer in Verilog to compute the sine and cosine of an angle θ. I will share the additional details later 15 Matlab and Mathematica, Verilog / VHDL Dec 2, 2017 Dec 2, 2017Terminato €53
Digital Design with Logic Devices It is a Project on Digital Design with Programmable Logic Devices. I will provide details later. 10 Verilog / VHDL Dec 1, 2017 Dec 1, 2017Terminato €44
pls help ac homewokr :'( i need log synchronous sequential circuit that solves a 64x64 maze using the right wall follower algorithm. how much???? u have 3 hours 8 Ingegneria, Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica Dec 1, 2017 Dec 1, 2017Terminato €71
Project for Gabriel G. Hi Gabriel! I'm working on my capsim simulation final and I got myself into a lot of debt and don't know how to fix it . I need a 70% on this and was wondering if you'd be able to help. Im currently on the 3rd round of 4. Would you be able to help me out? You were suggested by a classmate and was wondering if you'd be able to help me even though I already am on round 3. Thank... 2 Gestione Progetti, Telemarketing, Excel, Matlab and Mathematica, Verilog / VHDL, Dec 1, 2017 Dec 1, 2017Terminato €125
design and implementation of a MIPS CPU with Multi cycle Data path design and implementation of a MIPS CPU with Multi cycle Data path using the VHDL language 14 Programmazione C, Verilog / VHDL, Programmazione C++, Assembly, FPGA Nov 30, 2017 Nov 30, 2017Terminato €133
bubble level project the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board. In the video attached in the .zip, the operation of the project 8 Verilog / VHDL, FPGA Nov 29, 2017 Nov 29, 2017Terminato €70
VHDL code for Pipe lined MIPS-RISC (5 stage) processor.(Code for Un-pipelined will be given) I need you to do pipelining for the MIPS-RISC (5 stage) Processor. I will give you the MIPS processor code, all you need to do is pipelining. I will upload the file once go through it. If you are interested, I will send you the code and question for which code has written.” Deadline is " Dec-03-2017 " 12 Programmazione C, Ingegneria, Verilog / VHDL, FPGA, Parallel Processing Nov 29, 2017 Nov 29, 2017Terminato €146
logic analyiser and waveform viewer The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports one analog channel and one digital channel, with a single-level triggering. Only 8 bits of precision will be used for the analog channel. •Phase 1: Develop a minimal system that contains a PC, a microproce... 6 Elettronica, Verilog / VHDL, Microcontrollore, Architettura Software, Arduino Nov 27, 2017 Nov 27, 2017Terminato €273
interface hardware module with amber processor -- 2 - 27/11/2017 11:51 EST to implement an interface hardware module with amber processor 2 Verilog / VHDL Nov 27, 2017 Nov 27, 2017Terminato €179
Network traffic processing using two FPGAs I want to get throughput and latency results of network traffic(Ethernet packets processing) using two FPGAs, while i have throughput and latency results of using one FPGA, so i want to compare both these results. The results of using two FPGA chips should be better than using one FPGA. 6 Ingegneria, Verilog / VHDL, Ingegneria Elettrica, Amministrazione Rete, FPGA Nov 26, 2017 Nov 26, 2017Terminato €573
C++ based project - open to bidding cpp dependencies sorting out, we will provide you the structured file and the source code and you have to compile and run after sorting mugs from that 16 Elettronica, Verilog / VHDL, Programmazione C++, Arduino, RTOS Nov 25, 2017 Nov 25, 2017Terminato €92
Design and test a VHDL model for the instruction cache of a speculative out of order VLIW processor. Design and test a VHDL model for the instruction cache of a speculative out-of-order VLIW processor. Your VHDL code should have the following: - PC register updated on falling_edge of the clk to one of the following values: PC + VLIW_INST_SIZE, branch_target_PC, or EXCEPTION_ROUTINE_PC. PC register should be initialized to 1000 Hex when reset is active. Assume that the project ISA requires EXCE... 3 Verilog / VHDL Nov 25, 2017 Nov 25, 2017Terminato €307
System verilog - open to bidding I need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. Thanks 10 Programmazione C, Verilog / VHDL, Programmazione C#, Programmazione C++, FPGA Nov 23, 2017 Nov 23, 2017Terminato €9
interface hardware module with amber processor to implement an interface hardware module with amber processor 2 Verilog / VHDL Nov 23, 2017 Nov 23, 2017Terminato €25
single cycle 32bit mips verilog code -- 2 i need verilog code for 32bit mips single cycle it must contain instructions LW, SW, AND, ADD, ADDI, SUB, SLT, SLTI,b,BEQ, BNE, J, JAL and JR. and write a test-bench and stimulate and get the output waveform synthesis the code and submit to me 10 Programmazione C, Verilog / VHDL, Programmazione C++, Assembly, FPGA Nov 23, 2017 Nov 23, 2017Terminato €8
write a simple code for sample testing k Please check new schematic diagram in attached. And IC datasheet. Please write a simple code for sample testing 9 Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, Progettazione di Circuiti Nov 22, 2017 Nov 22, 2017Terminato €86
Using VHDL Implement a simple MIPS-2 RISC Processor It is a Project Using VHDL Implement a simple MIPS-2 RISC Processor. i will give the details later. 4 Verilog / VHDL, Ingegneria Elettrica Nov 22, 2017 Nov 22, 2017Terminato €87
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