Verilog / VHDL Lavori e Concorsi

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
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Progetto/Concorso Descrizione Offerte/Proposte Competenze Iniziato Termina Prezzo (EUR)
Circuit Simulation - 26/04/2018 05:56 EDT To simulate in LTspice or MultiSim a stair step wave within the sine wave generating circuit the circuit design using only analogue components like R, C, Op-Amp but no digital components like microcontroller. Task details will be provided to competed bidders only. If you have good command using above mentioned softwares then bid only. Pls note that the task is to complete in one day only not mor... 6 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, Progettazione di Circuiti Apr 26, 2018 Oggi6d 22h €32
Need an ARM processor programming expert - 26/04/2018 05:17 EDT Need someone who is efficient in ARM processor programming for an urgent assignment 5 Programmazione C, Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica Apr 26, 2018 Oggi6d 22h €49
Applications of Embedded C- Microcontroller MSP432 Project Hi, Need to complete few tasks of the Embedded C based programming project 10 Programmazione C, Elettronica, Verilog / VHDL, Microcontrollore, Programmazione C++ Apr 26, 2018 Oggi6d 17h €53
Verilog Code for Fast Fourier Transform I am having difficulties in finishing my final year project. I would like to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not... 14 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, FPGA Apr 25, 2018 Oggi6d 5h €114
Traffic Light Priority Control For Emergency Vehicles I want to design a circle through the Proteus program with the code. I have the code but I do not know the results show. 19 Ingegneria, Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica Apr 25, 2018 Apr 25, 20185d 19h €108
Verilog coding Verilog code of Simplified DES algorithm 6 Verilog / VHDL, Sicurezza Informatica, Architettura Software Apr 25, 2018 Apr 25, 20185d 18h €13
Convert a python program to vhdl Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog. 10 Python, Verilog / VHDL, Architettura Software, CUDA, Arduino Apr 24, 2018 Apr 24, 20185d 2h €248
Serializer & Desrializer Implementation using ZC706 and MTX___ Serializer & Desrializer Implementation using ZC706 and MTX 2 Verilog / VHDL, FPGA Apr 24, 2018 Apr 24, 20184d 18h €308
Modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo get servos' position by using fou... 5 Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, Software integrato, FPGA Apr 23, 2018 Apr 23, 20184d 15h €149
build a very simple MIPS code I need a simple MIPS code. I will send you the task. I need it in an hour. 9 Programmazione C, Java, Verilog / VHDL, Programmazione C++, Assembly Apr 22, 2018 Apr 22, 20183d 6h €16
FPGA Design and Asic Hi there Please check the document 10 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, FPGA Apr 21, 2018 Apr 21, 20182d 6h €28
FPGA Design Hi there Please check the document! 6 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, FPGA Apr 21, 2018 Apr 21, 20182d 6h €12463
Floating Point on DSP48E1 I need to implement floating point single precision algorithm (add,sub,mul,div)(standar IEEE754) on unit DSP48E1. I need a File Register on 48bit, a priority encoder on 32b, an exponent unit where is stock the sign and exponent and a sequencer(Delay Mealy automata) who give the comand to DSP. Can anybody help me? Thank you! 6 Verilog / VHDL, FPGA Apr 21, 2018 Apr 21, 20182d 1h €193
MIPS Computer Design by Verilog HDL I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL 18 Ingegneria, Verilog / VHDL, Assembly, Design Digitale, FPGA Apr 20, 2018 Apr 20, 20181d 6h €112
need to implement an ieee paper using verilog or vhdl. -- 2 would like to get the implementation of given ieee paper using verilog/vhdl within 15 days 10 Verilog / VHDL Apr 20, 2018 Apr 20, 20181d 3h €98
200418_Verilog All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours 4 Elettronica, Verilog / VHDL, Ingegneria Elettrica Apr 20, 2018 Apr 20, 20181d 1h -
Conceive SDR GnuRadio blocs This project aims at conceiving GNU-Radio blocs for receiving / transmitting modulated radio messages using Software Defined Radio (SDR). I need a software component lib called "gr-beaglesdr" of a software-defined radio receiver and transmitter combined with suitable hardware device BeagleSDR. It can be used to listen to or display data from a variety of radio transmissions and also send... 5 Linux, Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica Apr 20, 2018 Apr 20, 201821h 30m €914
Implementing Bit stuffing in verilog Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's 11 Ingegneria, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA Apr 20, 2018 Apr 20, 201817h 30m €24
Edge detection by using laplacian I want a freelancer for making a project who have strong knowledge of mpi and Openmp c++.If any one interested let me know so we can discuss it further Your task is to implement an initial serial version of the program, where it takes an image as an input and then produces an output image after applying the stencil matrix(Laplacian ) on the input image. Then, you should try to optimize the co... 1 Programmazione C, Verilog / VHDL, Architettura Software, CUDA, Programmazione C++ Apr 19, 2018 Apr 19, 201811h 10m €122
plc program and hmi design Simulation I have Program pLc program and Hmi design for academics project just to simulating the code with software need basic help 14 Ingegneria, Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica Apr 19, 2018 Apr 19, 20181h 6m €16
develop Simple SW to write on the IC Card/Server I have IC cards or integrated chip cards that i needed to write on them. So, i am looking for simple SW and support for successful testing of this beta version design. My design and solution is almost the same as access control however it has its own different use cases. So, let’s assume that I need to create SW solution for access control within a hotel or company using IC card i... 4 Programmazione C, Elettronica, Verilog / VHDL, Microcontrollore, Configurazione Circuiti Stampati Apr 19, 2018 Apr 19, 2018Terminato €233
translate C++ code in systemc. translate c++ code in systemc and implement constrained random verification methodology. 4 Programmazione C, Verilog / VHDL, Architettura Software, Programmazione C++, Very-large-scale integration (VLSI) Apr 19, 2018 Apr 19, 2018Terminato €22
build a software translate c++ code in systemc. and implement constrained random varification methodology. 1 Verilog / VHDL, Architettura Software, Programmazione C++, Very-large-scale integration (VLSI) Apr 19, 2018 Apr 19, 2018Terminato €16
Create a DLX Data Path Using VHDL Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code. 8 Verilog / VHDL, Microcontrollore, Architettura Software, Assembly, FPGA Apr 18, 2018 Apr 18, 2018Terminato €146
build a software translate a C++ code in systemc module. 3 Programmazione C, Verilog / VHDL, Programmazione C++ Apr 18, 2018 Apr 18, 2018Terminato €25
convert the C++ language code in systemc. you have to translate C++ code in systemc language. 3 Programmazione C, Verilog / VHDL, Architettura Software, Programmazione C++ Apr 18, 2018 Apr 18, 2018Terminato €27
Do VHDL project on the ModelSim I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir... 11 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, FPGA Apr 18, 2018 Apr 18, 2018Terminato €126
SoundLocator Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position 14 Java, Elettronica, Android, Verilog / VHDL, FPGA Apr 18, 2018 Apr 18, 2018Terminato €508
OpenCL FPGA Code modification I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [url rimosso, accedi per visualizzarlo] Please respond directly with any questions such as specific mining software and such. 6 Programmazione C, Verilog / VHDL, Crittografia, OpenCL, FPGA Apr 17, 2018 Apr 17, 2018Terminato €1847
Circuit at logism implement a digital circuit in Logisim for a door lock. 3 Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, Progettazione di Circuiti Apr 17, 2018 Apr 17, 2018Terminato €21
expert in vivado vhdl needed expert in vivado and vhdl needed asap 8 Ingegneria, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, FPGA Apr 17, 2018 Apr 17, 2018Terminato €21
digital logic design circuit in logisim there should be A and B inputs and the circuit should check if the A is divisible by B or not. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b). we have only 30 minutes to do. 9 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, Progettazione di Circuiti Apr 17, 2018 Apr 17, 2018Terminato €92
digital circuit in logisim we should draw a circuit in logisim. there should be 2 input like A and B. the circuit should check if A is dibisible by B or not. you should work with ALU. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b) 6 Elettronica, Verilog / VHDL, Microcontrollore, Ingegneria Elettrica, Progettazione di Circuiti Apr 17, 2018 Apr 17, 2018Terminato €17
Signal Peak Detector, Digital Design - Command Processor I am currently working on peak detector using VHDL entry (Modelsim and Xilinx), to design logic design in FPGAs to fulfill my free time. There are two parts, which are command processor and data processor. However, I have completed the data processor part, so only command processor left and I have no idea how to complete it. I plan to accomplish this task by next Sunday, 22nd April before I starte... 7 Ingegneria, Elettronica, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica Apr 17, 2018 Apr 17, 2018Terminato €38
Circuit in Logism Given two 4-bit integers, A and B, build a circuit that can outputs 1 if A is divisible by B, or 0 otherwise. It should be done using 4 bit ALU 8 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, Progettazione di Circuiti Apr 17, 2018 Apr 17, 2018Terminato €53
Logisim Digital Logic Design using four bit ALU, given two numbers A and B we need to find if A is divisible by B 15 Ingegneria, Elettronica, Verilog / VHDL, Ingegneria Elettrica, FPGA Apr 17, 2018 Apr 17, 2018Terminato €64
Neural Network on an FPGA I want to get a simple 3 layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware. 5 Programmazione C, Verilog / VHDL, Apprendimento Automatico, FPGA, Neural Networks Apr 17, 2018 Apr 17, 2018Terminato €121
CRYPTO MINING using VHDL in FPGA Details later.. I will check your BASIC.. And then recruit You 2 Verilog / VHDL, Ingegneria mineraria, Design Digitale, FPGA Apr 15, 2018 Apr 15, 2018Terminato €1710
programming mplab programm an fm receiver chip to be able a radio to work mp lab software using c or c++ everything exxplained in files that will be sent 18 Programmazione C, Verilog / VHDL, Microcontrollore, Programmazione C++, Arduino Apr 13, 2018 Apr 13, 2018Terminato €178
Experts on Communication system, Digital Signal Processing, and Matlab needed 2 - 12/04/2018 18:48 EDT Like mentioned above, I have many task on this. I need experts in this field who can help. I do not want someone who cannot work at a reduced rate since order is regular. Only people who is experienced in this field should bid. Thanks 6 Ingegneria, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, Ingegneria delle Telecomunicazioni Apr 12, 2018 Apr 12, 2018Terminato €25
Experts on Communication system, Digital Signal Processing, and Matlab needed Like mentioned above, I have many task on this. I need experts in this field who can help. I do not want someone who cannot work at a reduced rate since order is regular. Only people who is experienced in this field should bid. Thanks 3 Ingegneria, Matlab and Mathematica, Verilog / VHDL, Ingegneria Elettrica, Ingegneria delle Telecomunicazioni Apr 12, 2018 Apr 12, 2018Terminato €16
Mips, Verilog project Small project on computer architecture 20 Verilog / VHDL Apr 9, 2018 Apr 9, 2018Terminato €17
State Machine and Timing Diagram for Embedded System State Machine and Timing Diagram for Embedded System. More details to be provided. 17 Verilog / VHDL, Software integrato Apr 9, 2018 Apr 9, 2018Terminato €37
OS work ( Printing Service) In this work, I need a coder who will design a programming solution to a variant of the boundedbuffer producer/multi-consumer problem using semaphores. The main goal of the task is to get familiar with the basic concepts of InterProcess Communication (IPC) and threads. Your implementation will be based on the following: shared memory, locks, semaphores and threads. More details will be prov... 8 Programmazione C, Java, Verilog / VHDL, Programmazione C++, Programmazione Apr 8, 2018 Apr 8, 2018Terminato €27
Systemverilog TCPIP model Looking for a SystermVerilog TCPIP model which drives the MAC data to TCPIP DUT and analyze the data from DUT. Need some customization depending on the RTL. 3 Verilog / VHDL Apr 6, 2018 Apr 6, 2018Terminato €152
NS3 simulation using c++ and ubunto NS3 simulator NS3 simulation using c++ and ubunto NS3 simulator 5 Programmazione C, Linux, Verilog / VHDL, Architettura Software, Programmazione C++ Apr 6, 2018 Apr 6, 2018Terminato €298
ns3 project c++ ubunto needed i need this simulation for ns3 using c++ 4 Programmazione C, Linux, Verilog / VHDL, Architettura Software, Programmazione C++ Apr 6, 2018 Apr 6, 2018Terminato €193
Simple SCADA WEB page Web Page for monitoring data of sensor Login Security Historical reports Mobile COmpatibility Good Desing If you are interested you should write me a message saying you have experience in labview 9 PHP, Ingegneria, Verilog / VHDL, Architettura Software, LabVIEW Apr 6, 2018 Apr 6, 2018Terminato €148
Vhdl coding for a small project 1. Do some for loop in vhdl 2. Do some multiplication in vhdl 3. Add registers at input and output 4 Verilog / VHDL Apr 4, 2018 Apr 4, 2018Terminato €26
Serial Interface using Python Design a serial interface using Python for communication with FPGA. 5 Python, Verilog / VHDL, Interfaccia utente / IA, Architettura Software, FPGA Apr 2, 2018 Apr 2, 2018Terminato €26
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