VHDL DESIGNER

$30-250 USD

Chiuso

Pubblicato

quasi 3 anni fa

$30-250 USD

Pagato al completamento

• All the coursework has to be done in VHDL. Coursework handed in using another language will be marked as zero. • Coursework must be typeset. • Never use screenshots or photograph of code in your coursework. Typeset code within your coursework report using a monospace font (e.g. courier new). • Never use photographs of waveforms in your coursework. Use a proper screen capture tool to include a high resolution screenshot in your coursework. • The FPGA board is not required for this coursework • Vivado is not necessary for this coursework (syntax errors will not penalise the evaluation).

Verilog / VHDL

Rif. progetto: 30825393

Info sul progetto

11 proposte

Progetto a distanza

Attivo 3 anni fa

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11 freelance hanno fatto un'offerta media di $165 USD

@AbdullahWD

Is it still available?

$278 USD in 30 giorni

5,0

(9 valutazioni)

3,5

@vinendra77

Hi, I am Mtech graduate from IIT Roorkee and working on Hardware Description Languages Verilog and VHDL for the past 3 years. I have done many Digital system design projects using RTL design and FSM and had a working experience on FPGA boards. This is going to be my 30th project in freelancer and i promise to deliver the best as per your need in short time. You can refer to my portfolio item "sequence detection 101" designed using FSM and "Verilog code and VHDL code" written at https://www.freelancer.com/u/vinendra77 Thank you

$99 USD in 2 giorni

5,0

(9 valutazioni)

2,9

@yakub6542

Hello, I hove gone through the job posting then understood the requirements and very much interested to work with you . I have five plus years of experience in verilog/vhdl. I have successfully finished multiple projects in verilog/vhdl. I can help you with my experience and provide you good results. For more details please go through my profile. I hope we will work together. Regards, Yakub

$167 USD in 3 giorni

5,0

(2 valutazioni)

2,6

@NarendraNemo

Hi dear, I am master graduated in VLSI design and Embedded systems and also had 3 years of experience in developing algorithm especially mathematical functions, digital circuits and signal processing algorithm in verilog/VHDL and all these I can develop in matlab. So can you please initiate chat for discussion on your problems.

$75 USD in 2 giorni

3,9

(2 valutazioni)

2,0

@lsjlsj04127

Hello, Let's discuss the project through chat so we can get more details and start the project soon. Waiting for you. Thank you very much.

$140 USD in 7 giorni

0,0

(0 valutazioni)

0,0

@hivongmoi1234

Heloo you. I already read descriptions of your project. I think it very exciting . With 5 years experience design and code for FPGA board .Can i join with you to do this project?. please contact with me if you need any thing that useful for you. Thanhs for watching my bid.

$111 USD in 3 giorni

0,0

(0 valutazioni)

0,0

@RAJASEED

Hi We have 15 years of experience in developing design, verification using Verilog, VHDL and System Verilog. Expertise in FPGA Validation using Xilinx FPGA boards. Thanks

$140 USD in 7 giorni