Easy VHDL Problem

$10-30 CAD

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circa 9 anni fa

$10-30 CAD

Pagato al completamento

Hi, I need help with this in the next few hours. 1. Write a VHDL description for 32x16 RAM. This RAM has the ports: clk, en,rdwr,address, data_in,data_out. If rdwr = 0 and en =1 then the data stored in address will be loaded to data_out pins in the positive edge of the clock. If rdwr = 1 and en =1 then the data in the data_in bus will be stored in the specified address in the positive edge of the clock. If en = 0 then nothing will be done in the memory (no read and no write) 2. Write a test bench for this RAM. Thank you, Cheers, F

Verilog / VHDL

Rif. progetto: 7307034

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Attivo 9 anni fa

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@ee4raja

Hi I have 7+ years of experience in verilog and VHDL coding. Coding for your design requirement was completed just now. Ping me to discuss further and to deliver the code. -- Thanks and Regards ASR

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@loi09dt1

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@zarnescugeorge

Hello! How are you! I want to help you! I can give you the solution right away! Please send me a message! Have a nice day! .

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@dpappu131

hello ............................................................. i can do your work .......... thank you ........... waiting for your response ... regards ...........

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@elmennani

hello I can do the job in approximately 4 hours. if you are interesting to my offer please let me a message. regards!

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@tfrangieh

I am an embedded engineer and I program FPGAs for a living :) I have more than 6 years of experience in the field, and I know both VHDL and Verilog. Update: I have the module and testbench code ready and tested. Let me know if you need it.

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