Create a MIPS 5-Stage Pipeline Simulator

Given a set of instructions in binary, disassemble it into MIPS instructions. Create a 5 stage pipeline simulator. Produce a cycle-by-cycle simulation showing the processor state at each cycle. The processor state includes the contents of registers, buffers, cache, and data memory at each cycle. You do not need to implement exception/interrupt handling. files included: - Requirements: [login to view URL] - Sample input file: [login to view URL] - Sample output file: [login to view URL] - Disassembler and Current Simulator: [login to view URL]