System Verliog task available

$10-30 AUD

Chiuso

Pubblicato

più di 6 anni fa

$10-30 AUD

Pagato al completamento

I need someone who can do task on system verilog. Deadline is 2 days. I want someone who can start now. More details will be provided to interested freelancer

Electrical Engineering

Engineering

FPGA

Matlab and Mathematica

Verilog / VHDL

Rif. progetto: 15702231

Info sul progetto

5 proposte

Progetto a distanza

Attivo 6 anni fa

Hai voglia di guadagnare un po'?

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5 freelance hanno fatto un'offerta media di $29 AUD

@ahmedmohamed85

Dear sir please give me more details about the required task best regards

$30 AUD in 1 giorno

4,9

(504 valutazioni)

8,1

@raulbehl

Hello! I am an experienced Engineer and have been helping out many on this platform. It would be great if I could help you out. Thank you! Relevant Skills and Experience SystemVerilog and Digital Design - 4+ years Proposed Milestones $30 AUD - Final code

$30 AUD in 2 giorni

4,9

(89 valutazioni)

6,3

@hungfreelancer

I am verification engineer, I use systemverilog in my job. Chat with me to have more knowledge about my skills. Thank you

$20 AUD in 2 giorni

5,0

(8 valutazioni)

4,2

@kulwantsingh16

A proposal has not yet been provided

$30 AUD in 2 giorni

4,6

(15 valutazioni)

4,2

@dhruva1705

Hi I have 6 years of working experience in functional verification using systemverilog, First would like to understand you requirements. Thanks, Dhruva Relevant Skills and Experience Systemverilog. Proposed Milestones $35 AUD - would like to know about the task first.

$35 AUD in 5 giorni