I'm a digital design & verification engineer , i worked on projects such as
- PHY of SERDES (my GP)
- UART protocol
- spi protocol
- asynchronous FIFO
- create a UVM environment to verify the UART RX , TX and FIFO
I've a knowledge in analog modeling as in my graduation project i did a modeling for CDR circuit .
- i 've knowledge in system verilog assertions, constrained randomization , regression testing, functional code coverage
- i've knowledge in modeling with CPP using DPI with system verilog
- i'm familiar with verdi , vcs , spyglass , design compiler , formality , prime time , questasim as well as writing tcl script for each one