Vijayvithal J.

Major Skill sets are. * Architecture analysis and Digital design (Verilog/ASIC/FPGA) * RTL coding, Verification, Validation and Synthesis. * Languages: Verilog, Tcl, Perl * # Domains: =============== 1. Communication (PCIe, Ethernet, PCS, MAC, Serdes, WLAN ), 2. Cryptography, 3. Video & Display Technologies 4. DSP, 5. SoC and subsystem development Keywords: Verilog, ASIC, FPGA, Synopsys, Xilinx, Altera, Intel, Vivado, Quartus, Modelsim, VCS, Synthesis, Perl, Tcl. ARM, RISC-V, VHDL, BSV, cocotb # Work Experience: ================== Technologies worked on: 1. Networking and communication: Ethernet Subsystems, Wireless LAN, DOCSIS, DTV. 2. Cryptography, 3. Display Subsystem, Video Processing 4. Microcontrollers & Peripherals 5. ARM and RISCV based subsystem design Verilog/VHDL/SystemC/SystemVerilog, Perl, Tcl, Python(cocotb, myHDL). Tapeout's: Contributed to the tapeout of over a dozen ASIC's Why Hire Me? ============== If you ideal candidate is someone who can take your Idea for an IP/Chip and independently or with minimal day to day supervision, drive the entire process from 1. Studying the Product Requirements/Industry Standards. 2. Creating and proposing a suitable Architecture and work plan. 3. Defining the Micro-architecture and driving Verification 4. Implementing and verifying the design. 5. Validating the design. Then I am the right candidate for you. My successful contracts are a mix of 1. Clients expecting and End to End(Steps 1-5 above) Design delivery. OR 2. Clients expecting 1-5 from me and also requiring me to supervise and guide their junior staff for 4 & 5. Employment Details. ([login to view URL]) ================ 1. Texas Instruments: (10 Years) RTL Lead. 2. Intel(6 Years) Architect Ethernet Subsystems. 3. Dyumnin Techologies/Dyumnin Semiconductor (3 years) Co-Founder, Engineer. 3.1. IP Design( Networking, Gaming systems, Cryptography) 3.2. Design automation related tools and products. 3.3. IP Portfolio, Design tools, Design consultation & RTL to Gates services for complex designs.