VHDL test procedure and test bench implementation

Chiuso Pubblicato 1 anno fa Pagato alla consegna
Chiuso Pagato alla consegna

VHDL test procedure and test bench implementation

Verilog / VHDL FPGA Ingegneria Ingegneria Elettrica Matlab and Mathematica

Rif. progetto: #34687469

Info sul progetto

5 proposte Progetto a distanza Attivo 1 anno fa

5 freelance hanno fatto un'offerta media di ₹25000 per questo lavoro

athulb

Hi client, Thank you for taking time to read my proposal. You are welcome review my profile to know more information. I have 4 years of experience in VHDL. Im familer with making counter, up counter , download coun Altro

₹25000 INR in 7 giorni
(13 valutazioni)
3.8
nikitaberezin

I'm verification engineer with 10 years of experience. Will provide good level of testbench for your design.

₹12500 INR in 7 giorni
(2 valutazioni)
2.9
nivashDVE

Hi, I am Senior verification Engineer and currently I have 4 year experience on ASIC/FPGA ,VHDL . I developed Test Bench for AXI interconnect , APB and SPI bridge from scratch . I developed system verilog assertion f Altro

₹25000 INR in 7 giorni
(0 valutazioni)
0.0
grapessoft

Hi Greetings! I am available right now for the project discussion and can start the project on an immediate basis. I have understood your project requirement I have7++ experience in design and development. I can ha Altro

₹37500 INR in 7 giorni
(0 valutazioni)
0.0