Verilog, SV & UVM Trainer

I am a Verification Engineer. I have a good expertise of UVM, SV, and Verilog. I also like to teach students.

Hi, I'm a Digital Design Engineer. I have a good understanding in Verilog, SV and UVM. I can teach you so that you can have good understanding in all these three subjects. I can also include some projects that will help you to understanding more efficiently.