Reed solomon encoder and decoder

Dear sir I have more than 10 years experience in digital systems design using verilog, please check my profile, also please message me so that we can discuss Best regards

Hi I am expert in verilog. I can do this job for you. Please see my previous FPGA based projects. Contact me to discuss further details please.

Hi, I hope you are doing well and enjoying digital design. I believe implementing a design right form modeling until verifying it on an FPGA is always a very special experience. Regarding your project, I had built a fully-verified tens of RTL projects and implemented them on Spartan 6. Throughout my 3+ years of experience in the field, I had the joy of designing and implementing a part of LTE's physical layer right from the Matlab model, through RTL coding, simulations, and back-end stages. I also built many other designs such as a MIPS processor design, Can satellite that composed I2C, UART, and many FIFOs to handle data. All my designs were verified successfully on either Xilinx's Spartan S6, S3, or Altera's Cyclone V FPGA. I would love to hear your thoughts and requirements for the delivery soon. Have a good night :))

Hello I am an Electrical Engineer and have good skills in verilog and FPGAs. I can develop the code and testbench for reed solomon encoder and decoder as per your requirements. I am familiar with xilinx and modelsim softwares. Thanks

Hi We Rogtech, having 10+ years of experience in VerilogHDL programming, verification and implementation. Regarding your project,. We have working code for Reedsolomon encoder and decoder in simulation using Modelsim and implementation in Xilinx Zync7000 FPGA. Kindly contact us, we should be able to deliver the coding in a day or two. Thanks and Regards, Rogtech

I have good experience in verilog programming.. Presently I am doing project on image encryption with AES algorithm

I have worked on Ethernet 400G, it was having RS(544,514). I have made encoder as well as decoder for the same. I would be happy to work on this project. Besides I am having a good knowledge of verilog so I can complete your job as soon as possible.