Design of D flip flop in Cadence virtuoso 180nm Technology

Hello, I am an electronics engineer having experience in cadence design suite for more than 3 years. Relevant Skills and Experience Digital deign, analog design Proposed Milestones $111 CAD - DFF Design in CMOS 180 nm

Designing 3 flip flop circuits and compare between them in terms of power, delay and area. The designs to be done in 180 nm technology node and using Cadence Virtuoso. Relevant Skills and Experience I am a Nanoelectronics with 4 years of experience in designing digital and analog circuits in submicron technology nodes using Cadence tools. Proposed Milestones $100 CAD - 1st Circuit $50 CAD - 2nd Circuit $100 CAD - Final Delivery Additional Services Offered $50 CAD - I can write you a decent report / paper containing the results. $75 CAD - Step by step illustrations of the whole design process and how did it gone. The price are negotiable and I can finish the requirements in 4 days.

Hi, I do work in electronics and VLSI field. I can accomplish your project/research in 7 days as I have already designed different types of flip-flops in TSMC 130 nm node with layout having LVS and DRC clean I have Cadence Virtuoso 6.1.6 also 12.3 to work with 180nm if u can send me the PDK or I can provide all research files using TSMC 130 nm node For post layout simulation I will use Hspice. Can provide dff simulation in ADE or Hspice Waiting for your response.... Thanks in advance...

I have well experienced in doing such kind of jobs....................... Relevant Skills and Experience verilog/vhdl, cadence Proposed Milestones $333 CAD - i will do my level best

Sir, I am an experienced electronics engineer in a leading electronics company. Relevant Skills and Experience I developed so many Embedded boards, FPGA boards, SoC boards, Microcontroller boards using ORCAD Cadence and written codes in C, VHDL, Vivado. Proposed Milestones $250 CAD - For complete schematic CADENCE I will design schematic in Cadence Virtusa for low-power high-speed flip-flop for given states. Thanks

I just work for a project like that last month.

Doing a survey of related work for low-power and high speed D-FFs. (Full custom) design of 3 FFs in cadenece. A comprehensive comparison between them with regard power, timing & no. of transistors Relevant Skills and Experience I have already implemented a D-FF (Master slave) in cadence before as a part of 4-bit LFSR project (you can see the full report in my portfolio) So, I'm very familiar with the topic. Proposed Milestones $50 CAD - Shemactic design entry for the 3 FFs $10 CAD - pre-layout simulation (using Spectre S) $100 CAD - Layout entry (probably with 2 layers of metal) $20 CAD - DRC (using Diva) $20 CAD - LVS $10 CAD - post layout simulation (using Spectre S) $30 CAD - documenting a full comparison Additional Services Offered $60 CAD - RTL implementation (using verilog in Xilinx ISE) and FGPA prototyping for the 3 designs I want to ask about the required technology for the design.

Hello I've experience of working with Cadence tools for a long time as a schematic and layout engineer and your job seems interesting to me. I'm hopeful that I can complete this project as you required. Thanks Mahmudul