12/24 hr clock implementation in VHDL

Hello, I am Digital Design Engineer. I am working on vivado tool, diamond tool , modelSim and libero. I have knowledge in verilog ,VHDL language and using it in many projects. I am looking forward to working with you

Hi there I am expert at coding verilog/VHDL. I can design the clockmodule as your descriptions in a days even in hours. Lets chat and discuss the details.