Build a 64-Bit Radix-16 Booth Multiplier Based On Partial Product Array Height Reduction project

Dear sir I have more than 10 years experience in digital please message me so that we can discuss more details

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

I am an experienced digital design engineer with VHDL and Xilinx knowledge. As part of this project I'll design the multiplier against the provided spec and verify its functional operation in ModelSIM. Drop a line over chat if you have any questions, kind regards

Hi, I hope you are doing well and enjoying digital design. Throughout my 2+ years of experience in the field, I had the joy of designing and implementing a part of LTE's physical layer right from the Matlab model, through RTL coding, simulations, and back-end stages. I also built many other designs such as a MIPS processor design, Can satellite, and a UART transmitter and receiver. All my designs were verified successfully on either Xilinx's Spartan S6, S3, or Altera's Cyclone V FPGA. The process of building some RTL design differs according to the final destination of the project. For instance, a design for ASIC tape-out will have other methodologies of debugging and verification than if it's for FPGA. Subsequently, I would like to know which methodology of testing you would prefer me to adopt, simulations or UVM environments. It is up to you really. I am fine with both. I would love to hear your thoughts and requirements for the delivery as well. I wish you get the best out of this project. - Eslam

5 days