bubble level project

Chiuso Pubblicato 6 anni fa Pagato alla consegna
Chiuso Pagato alla consegna

the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board.

In the video attached in the .zip, the operation of the project

FPGA Verilog / VHDL

Rif. progetto: #15762690

Info sul progetto

5 proposte Progetto a distanza Attivo 6 anni fa

5 freelance hanno fatto un'offerta media di $74 per questo lavoro

sourindu

A proposal has not yet been provided

$55 USD in 4 giorni
(1 Recensione)
2.3
alexstyle

The offer is purely indicative and we could discuss the details by chat.

$35 USD in 10 giorni
(0 valutazioni)
0.0
chinhtranduc

I have experience working on FPGA kits such as Xilinx Artix 7 development board, Numato NESO,.. Relevant Skills and Experience FPGA, Verilog/VHDL, image processing, C/C++ Proposed Milestones $35 USD - please add more Altro

$35 USD in 1 giorno
(0 valutazioni)
0.0