ASIC Design-Verification article on UVM

Chiuso Pubblicato 6 anni fa Pagato alla consegna
Chiuso Pagato alla consegna

Dear ASIC Verification Experts,

I am looking for ghost writer who is from ASIC verification background.

I want a unique article which tries to explain why we need to use UVM (Universal Verification Methodology). The title of the article will be similar as this. "If SystemVerilog is so good, why do we need the UVM? ". The article needs to start by answering this question in title. The target audience will be experts in System-Verilog and knows concepts of UVM. The article needed to be original and meaningful content.

Please bid with your experience in UVM so that I can provide the project to you quickly.

You can expect several article writing project if the first one happens good. Budget per article $100.

Thankyou.

Verilog / VHDL

Rif. progetto: #15931489

Info sul progetto

3 proposte Progetto a distanza Attivo 6 anni fa

3 freelance hanno fatto un'offerta media di $100 per questo lavoro

kulwantsingh16

5 year experience in UVM

$100 USD in 7 giorni
(14 valutazioni)
4.2
mze5583fac62088c

Hi, my name is Zeeshan. I would love to write articles on UVM. Please let me know how many words should be in this article. Relevant Skills and Experience I am MS Electrical Engineer with the embedded systems as my s Altro

$100 USD in 3 giorni
(0 valutazioni)
0.0