System Verilog Project 5
$30-250 USD
Pagato alla consegna
ALU
The ALU should be coded using these integer operations *, +, -, and /.
Register File
The register file must be implemented in a separate module.
Hex display
The hex display must be implemented using a function that converts
digits to 7 segment display segments.
Rif. progetto: #17189483
Info sul progetto
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Hello! Please check my profile and reviews to know a bit about me and my work. I have helped many students in the past and would be happy to help you as well. Thank you!
15 freelance hanno fatto un'offerta media di $131 per questo lavoro
Dear sir I have more than 10 years experience in digital system design using system verilog, please check my profile, also please message me so that we can discuss Best regards
Hello. How are you? I am a Cpp expert. It's my top skill. What i want is not money. I just want to get more reviews. Let's chat about your project. Thank you
Hi, I am a professional electrical engineer. I am an expert in designing and simulating digital systems and writing Verilog and VHDL codes I also have both modelsim and Quartus to test and confirm working code. You can Altro
Fresh graduate Nano-electronics engineer. Published a scientific paper. Interested in Digital circuit design (VERILOG coding and ASIC/FPGA implementation) Send me a message to discuss further details.
I have made an ALU for a pipelined ARM processor with complete instruction sets. Are you working on a specific processor architecture like ARM or it is the one in the pdf file? The deadline I made it 3 days till I m Altro