viterbi decoder

Chiuso Pubblicato Oct 27, 2014 Pagato alla consegna
Chiuso Pagato alla consegna

write a parallel viterbi decoder + sequential decoder in verilog (vivado) asap!

Architettura Software Verilog / VHDL

Rif. progetto: #6649155

Info sul progetto

6 proposte Progetto a distanza Attivo Dec 3, 2014

6 freelance hanno fatto un'offerta media di $401 per questo lavoro

zarnescugeorge

I can help you right away! Have a nice day! .

$277 USD in 5 giorni
(46 valutazioni)
5.8
botondkireivw

Hello I have a Viterbi decoder core allready written. I will send you the IP core and its documentation as you create the milestone for this project. I will release sample code for you, if you wish. Regards, Bot Altro

$250 USD in 10 giorni
(19 valutazioni)
4.9
saf818

Hi I have have worked on Viterbi. Let me know if i can be of help Best Regards Syfar --------------------------------------------------------------------------------------------------------------------------- Altro

$600 USD in 7 giorni
(3 valutazioni)
2.5
Besha1987

With extensive experience in design for wireless communication systems and large background in different decoders, I can implement your decoder with efficient area and throughput

$500 USD in 20 giorni
(0 valutazioni)
0.0
RAJCDAC

Dear Sir, i am ready to take on the task,we have expertise using Xilinx and ALtera FPGA,will complete as per the deadline.

$526 USD in 12 giorni
(0 valutazioni)
0.0
gaonanzhe1987

Hi,Client! I'm very happy to bid to you! Please give me the chance of take your job. I'm already for your job. I am professional of the Communication Engineering. If you select me, you will get highest service fro Altro

$250 USD in 5 giorni
(0 valutazioni)
0.0