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vhdl coding

I need this done in Vivado Design Suite for VHDL.

1. Write a testbench and simulate vga_controller.vhd. Just simple simulation to see that it works as expected (simulate the clock, hsync and vsync).

2. Write a testbench and simulate ram.vhd. Just something simple to see that it works.

Competenze: Elettronica, FPGA, Matlab and Mathematica, Microcontrollore, Verilog / VHDL

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Sul datore di lavoro:
( 1 recensione ) attock, Pakistan

ID Progetto: #11983721

Assegnato a:

$25 USD in 1 giorno
(111 valutazioni)
6.4

7 freelance hanno fatto un'offerta media di $147 per questo lavoro

ahmedmohamed85

A proposal has not yet been provided

$250 USD in 1 giorno
(256 Recensioni)
7.4
ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Più

$100 USD in 0 giorni
(42 Recensioni)
5.3
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zoltankulcsar

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dangluonghoangvu

Hi you, I am working on Arrive technologies VietNam, so i think i have enough tools to work with you in this project? Please contact me if you need more information about my tools thanks Vu

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