I need this done in Vivado Design Suite for VHDL.
1. Write a testbench and simulate vga_controller.vhd. Just simple simulation to see that it works as expected (simulate the clock, hsync and vsync).
2. Write a testbench and simulate ram.vhd. Just something simple to see that it works.
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Hi you, I am working on Arrive technologies VietNam, so i think i have enough tools to work with you in this project? Please contact me if you need more information about my tools thanks Vu