SystemVerilog - Complete Single-Cycle Processor + Synthesis

Chiuso Pubblicato 6 anni fa Pagato alla consegna
Chiuso Pagato alla consegna

I need help completing a Single Cycle RISC-V datapath and control using System Verilog.

What I need:

- A report including how different instructions have be to implemented. The

document contains all the necessary modifications in the datapath to add all the instructions.

- Modify the code to implement all the instructions.

Ingegneria Elettrica Elettronica Ingegneria Verilog / VHDL

Rif. progetto: #16333530

Info sul progetto

5 proposte Progetto a distanza Attivo 6 anni fa

5 freelance hanno fatto un'offerta media di $48 per questo lavoro

raulbehl

Hello! Please check my reviews and profile to know more about me and my work. I have designed processors before and should be able to do it for you as well. Thank you!

$35 USD in 3 giorni
(87 valutazioni)
6.3
karakaalekhya

A proposal has not yet been provided

$25 USD in 6 giorni
(0 valutazioni)
0.0
ductt

depend on how complex of your instructions, and number of them, finish time maybe shorter Relevant Skills and Experience worked in large company, expertise in Verilog design for GPU, Shader processor

$45 USD in 2 giorni
(0 valutazioni)
0.0