Implement RSA algorithm synthesized code (512 bit) in Verilog
₹600-1500 INR
Chiuso
Pubblicato circa 6 anni fa
₹600-1500 INR
Pagato al completamento
Hi,
I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption.
- Encryption data output size can vary from 16-bit to 512 bits.
- Prime number generation: two random prime number generated through LFSR and should be
stored in FIFO
- For every iteration different public and private key pairs should be produced.
Kindly contact know if this can be done within 2 days of time frame. We can discuss about budget.
Thanks,
Jayesh
I could locate 4h per day to work on this project. expert on Verilog design & FPGA. Available platform for testing & simualtion.
Relevant Skills and Experience
worked in large company, expertise in Verilog design for GPU/Ethernet, also implement FPGA system for 25Gs Ethernet