Filter bank Simulink and VHDL implementation
£20-250 GBP
Pagato alla consegna
My aim of this work is to see how it would be done from a different point of view.
What I would like to be done is:
* Check the Simulink model to see if that's done correctly.
* Finish minimum resource version in filter bank Simulink model (just add memory and switch between memory in each cycle and do DFT).
* Implement the minimum resource filter bank in VHDL in the simplest possible way. It can be done on HDL designer or Simulink VIVADO Signal Generator.
* Create a word file with short explanations how VHDL model works and add guidelines what algorithm was used to implement DFT.
* Do a bit-true simulation in order to confirm that VHDL model works the same as the Simulink minimum resource version.
Filter bank specification is given in [login to view URL] file
Number of users: 4
Sampling frequency: 16kHz
Rif. progetto: #18292582
Info sul progetto
4 freelance hanno fatto un'offerta media di £167 per questo lavoro
Dear sir I have more than 10 years experience in digital design using FPGA please message me so that we can discuss
I have well experienced in doing such kind of jobs...........................................................................................
I am expert who understands the value of time. I pride myself in my attention to detail. I am very hard working and aim to deliver in less time than quoted. I want to make you, my employer happy without changing my bid Altro
Dear sir, I have experience in both simulink and Hdl . You will your solution in both Matlab and modelsim.