Filter bank Simulink and VHDL implementation

Chiuso Pubblicato 5 anni fa Pagato alla consegna
Chiuso Pagato alla consegna

My aim of this work is to see how it would be done from a different point of view.

What I would like to be done is:

* Check the Simulink model to see if that's done correctly.

* Finish minimum resource version in filter bank Simulink model (just add memory and switch between memory in each cycle and do DFT).

* Implement the minimum resource filter bank in VHDL in the simplest possible way. It can be done on HDL designer or Simulink VIVADO Signal Generator.

* Create a word file with short explanations how VHDL model works and add guidelines what algorithm was used to implement DFT.

* Do a bit-true simulation in order to confirm that VHDL model works the same as the Simulink minimum resource version.

Filter bank specification is given in [login to view URL] file

Number of users: 4

Sampling frequency: 16kHz

Ingegneria Elettrica Ingegneria FPGA Matlab and Mathematica Verilog / VHDL

Rif. progetto: #18292582

Info sul progetto

4 proposte Progetto a distanza Attivo 5 anni fa

4 freelance hanno fatto un'offerta media di £167 per questo lavoro

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using FPGA please message me so that we can discuss

£200 GBP in 3 giorni
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thasleemkamila

I have well experienced in doing such kind of jobs...........................................................................................

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schoudhary1553

I am expert who understands the value of time. I pride myself in my attention to detail. I am very hard working and aim to deliver in less time than quoted. I want to make you, my employer happy without changing my bid Altro

£150 GBP in 3 giorni
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waqarahmed190

Dear sir, I have experience in both simulink and Hdl . You will your solution in both Matlab and modelsim.

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