Verilog/VHDL blocks for Virtex-7 FPGA

Dear sir I have more than 10 years experience in digital design using Xilinx FPGA, i can do all the required 5 Tasks perfectly, please message me so that we can discuss Best regards

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

A Data Scientist with experience in Python, R programming, R Shiny, R studio and anything related to data science and python Master in Engineering, Electrical and Electronic Engineer, who is dynamic, reliable, resourceful, committed and organized with enthusiastic approach to succeed with a pleasant attitude. Possessing excellent analytical skill and good research background. I have successfully completed IELTS with an overall band of 7 and have a good proficiency in English 10 Years Experience in Data Science Data Visualization Power BI Tableau Business development Anything on R programming COMPLETED PROJECTS • FM radio. • VHDL Design of an Up/Down Counter. • Design of Up/Down Counter using PIC. • Duck Shooter Program using C. • Pointer movement controller on 2-dimentional axis using C. • LCD display Manipulation projects including: o Text Display o Volt-Meter • Analog to Digital Conversion (8-bit). • Sound to Light Color Organ Design and Development. • Minesweeper Player Creation using PIC. • Simulation of an End to End Communication System with MATLAB. • (BENG Individual Project) (MENG Part A). • (MENG Individual Project) (MENG Part B). • (MENG Group Project).

I have 10 years of experience in design and verification using Verilog. This task is quite simple with me. Please message me. Best regards.

Hi! I have successfully finished a lot of FPGA projects, one of them found here, on Freelancer.com, you may find my employer feedback. Please contact me via chat to discuss implementation details of your requirements.

Hello I have over 10 years experience using Xilinx devices and working with Vivado. I would be happy to supply some example code that I have produced if that would be of interest. Thanks Jon

I've more than four years of industrial experience in FPGA, ASIC Design using VHDL, Verilog/Systemverilog. I've done multiple projects on Communication protocols and high speed signal processing. I've used multiple RAM inference models ( SDP,TDP etc) given by Xilinx.

I am working on Xilinx FPGAs for 3 yrs from now. Zynq and UltraScale+. Get the smallest block of problem. I will provide the solution. If you liked my way of working. We will go further.

Hi Sir, I have five years of experience in FPGA design. And I have strong skill in Verilog/VHDL coding. I have certification of Xilinx about design methodological. Below are some of the skill that I worked before: - PCIe - DMA - Carrier Ethernet - Switch, Router, TCP/IP, - Dynamic reconfig transceiver. - FPGA acceleration - Cryptography. - Matlab/DSP - ................ More detail, Could you please share your email, I will send xpm wrapper that I wrote before. Thanks, Vu