SERDES RTL DESIGN
minimo $50 USD / ora
I'm looking for an experienced SERDES engineer to design a SERDES PCS on ASIC. This PCS will be connected to a PHY(PMA) IP, encoding the data with 8b10 protocol and then transmitting (no receiving) the data out through the PMA, 5Gbps. The data will be received by a Xilinx FPGA GTH Transceiver and then decoded. Therefore the PCS logics shall be compatible with the GTH Transceiver.
Your tasks are
1. Write the PCS RTL code
2. Provide a compatible GTH transceiver configuration/RTL.
3. Provide guidance on verification of the whole link channel.
Rif. progetto: #18004382
Info sul progetto
9 freelance hanno fatto un'offerta media di $56/ora per questo lavoro
Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Altro
I am Senior Electronic Engineer with advanced knowledge of digital signal processing, and experience in the design of embedded systems in real time implemented with DSP, FPGA and Microcontrollers. In my experience i Altro
Hello, I see that you’re looking for an experienced SerDes engineer to include SerDes block into ASIC, and would like to offer our team to get this done efficiently and in reasonable time. We are a team of elect Altro
I have successfully done communication using GTX, and I have exposure to GTH also. I have knowledge of PMA + PCS. I can do your project.
1.0 year of experience in Analog layout design 3.0 years of experience in FPGA and Embedded System Familiar with device driver development with many interfaces (I2C, UART, SPI, AXI protocol), extensive knowledge abo Altro