Cyclic redundancy check error detection code

Cancellato

14 freelance hanno fatto un'offerta media di $130 per questo lavoro

ahmedmohamed85

HI, I dont know what happen, i was going to deliver the files but i found the project deleted, please tell me whats the problem Best regards

$120 USD in 1 giorno
(256 valutazioni)
7.4
$200 USD in 3 giorni
(82 valutazioni)
6.1
raulbehl

Hello! Please check my profile/reviews to know a bit about me. It would be great if I could help you out. Thank you!

$30 USD in 5 giorni
(31 valutazioni)
5.2
rohi1710rohi1710

Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TS Altro

$222 USD in 7 giorni
(4 valutazioni)
4.5
SqUa11

Hello, My name is Mohamed. I have 5 years experience in Digital Design and HDL. I checked your project description about implementing verilog code for error detection for CRC. I can guarantee to deliver high qualit Altro

$200 USD in 3 giorni
(15 valutazioni)
3.9
ngochan1405

Hi, I have 7+ years experience working in Hardware/Embedded System design field. I'm expert in Verilog/VHDL and familiar with Xilinx/Altera FPGAs as well as their tools. I can surely help you. Do you want to make a Altro

$120 USD in 3 giorni
(6 valutazioni)
3.4
kulwantsingh16

A proposal has not yet been provided

$166 USD in 5 giorni
(4 valutazioni)
3.3
jasnaikaran

Hello, I am an electronics engineer having experience of FPGA based system design for more than 5 years.

$55 USD in 2 giorni
(2 valutazioni)
2.9
piyapujara

A proposal has not yet been provided

$111 USD in 3 giorni
(0 valutazioni)
0.0
hemal1993

Hi, I can do this in 3 days. Contact me with your requirements. Have a great day. Hemal

$77 USD in 3 giorni
(0 valutazioni)
0.0
$155 USD in 3 giorni
(0 valutazioni)
0.0
aahmed88

I am AbdulRahman, I have more than five years experience in RTL implementation using Verilog/VHDL. I have implemented CRC code before and I have good experience with communication modules.

$35 USD in 3 giorni
(0 valutazioni)
0.0
yemelitc

Hello, a non-buggy implementation of the cyclic redundancy check in Hardware can be non-trivial, but I am willing to put in the effort. I will provide the Verilog testbench that demonstrates the working of the hardware Altro

$70 USD in 10 giorni
(0 valutazioni)
1.3
gsfikas

Several years of experience in signal processing algorithms. More than 5 years of experience in verilog coding for ASIC development

$222 USD in 5 giorni
(0 valutazioni)
0.0
svserge50

I develop VERILOG programs during one year. And already got skills in assembly languages programming.

$155 USD in 15 giorni
(0 valutazioni)
0.0