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    3,483 online vhdl verilog project bid lavori trovati, prezzi in EUR
    viterbi decoder Terminato left

    write a parallel viterbi decoder + sequential decoder in verilog (vivado) asap!

    €331 (Avg Bid)
    €331 Offerta Media
    7 offerte

    Using VHDL to design a microcontroller peripheral in Quartus software, (Altera).

    €763 (Avg Bid)
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    12 offerte

    We are looking for someone to design our website using the WebFlow platform. We want the site to give users a test and based on their answers redirect them to a page with a list of political candidates that match their beliefs.

    €404 (Avg Bid)
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    31 offerte

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €149 (Avg Bid)
    €149 Offerta Media
    11 offerte

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €124 (Avg Bid)
    €124 Offerta Media
    2 offerte

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    €353 (Avg Bid)
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    2 offerte
    Vhdl LCD finctional 1 giorno left

    In ready projekt on vhdl (tic tac toe game) I need to add state od the gamę on LCD [accedi per visualizzare l'URL]

    €27 (Avg Bid)
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    5 offerte

    I require a developer to set up a cron job that calls the Goog...job that calls the Google DBM and DCM Reporting APIs and saves csv reports on our server daily. This will require knowledge of the following: [accedi per visualizzare l'URL] [accedi per visualizzare l'URL] thank you

    €114 (Avg Bid)
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    5 offerte

    Hi there, I am looking for someone who knows how to utilise GitHub Desktop for automated version control of educational resources that are in Word, Excel and PowerPoint formats. These documents are to be saved on our company's server and I want to make it as simple and automated for my team members so all that they have to do is save in the right folder (this is the extent of their IT skills...

    €61 (Avg Bid)
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    1 offerte
    DSP48E1 help Terminato left

    Hi! I need some help with DSP48E1 verilog instantiation.

    €3 / hr (Avg Bid)
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    5 offerte

    I need to write a VHDL code for transfer data from 2 zedboard using ethernet without using a zynq-processor

    €177 (Avg Bid)
    €177 Offerta Media
    12 offerte
    I want clients Terminato left

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

    €15 (Avg Bid)
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    2 offerte

    German English file. please bid with the least price

    €14 (Avg Bid)
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    17 offerte

    I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

    €16 / hr (Avg Bid)
    €16 / hr Offerta Media
    11 offerte

    Build a Taxi App for me. A good user interface. Simple, responsive and user friendly android application needed. Budget - Max of 20,000/-. Thanks a lot.

    €428 (Avg Bid)
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    32 offerte

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    €131 (Avg Bid)
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    7 offerte

    Disclaimer: Price is fixed. Number of articles and pages required are fixed. Non Negotiable. Bid only if you are okay with it. I need you to write 5 different articles of 25 pages each (on MS word). Bid with answer to 4*5 in your message as an indicator that you read the requirement.

    €13 (Avg Bid)
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    11 offerte

    add memory protection into the operating system, This project needs both hardware and software knowledge, you will be creating / implementing OS functions on the PicoBlaze, programming in assembler. You may also need to modify the hardware using VHDL.

    €424 (Avg Bid)
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    11 offerte

    Hello guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table in the files section. Thank you a lot...

    €94 (Avg Bid)
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    1 offerte

    Hello guys I...cache memory). I would comments on the code and the resulting image as deliverables. 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works. Again comments on the code please. P.S.: 8 by 8 vhdl integer divider I attach the image table in the files section. Thank you a lot for your bidding :)

    €21 (Avg Bid)
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    3 offerte

    écrire un code vhdl , pour DE0 nano , permettant de lire la température a partir d'une entrée analogique avec un LM19 et en sortie il faut emmètre des son avec un buzzer ( différent fréquence en fonction de la température )

    €31 (Avg Bid)
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    2 offerte

    Hello guys I will ...language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works I attach the image table in the files section. Thank you a lot for your bidding :)

    €24 (Avg Bid)
    €24 Offerta Media
    3 offerte

    I need help with the structural in Xilinx. I will give you full details. Regards

    €20 (Avg Bid)
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    24 offerte

    ...Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but having Good experience and great expertise in their specified field

    €32 (Avg Bid)
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    112 offerte

    ...working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • i need you to check if the clock frequency is correct. Can you please help me , i need go deliver the project asap :).. We can

    €49 (Avg Bid)
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    1 offerte
    verilog project Terminato left

    verilog coding using putty or terminal. if you are interested i will give more information.

    €115 (Avg Bid)
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    27 offerte
    System verilog Terminato left

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    €88 (Avg Bid)
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    9 offerte
    ADC - VHDL Implement Terminato left

    Implement an AD2949 IC input block and some more

    €452 (Avg Bid)
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    12 offerte
    verilog project Terminato left

    mtech Verilog project

    €18 (Avg Bid)
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    19 offerte

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    €153 (Avg Bid)
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    7 offerte

    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    €2405 (Avg Bid)
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    15 offerte

    page has 7 columns of which 2 are buttons and 2 are check marks page must have a search feature Sample of the mysql code is select [accedi per visualizzare l'URL],[accedi per visualizzare l'URL],scid_gsm.gsm_number,dayname(balance.balance_date), time(balance.balance_date),[accedi per visualizzare l'URL] from sim_bank.scid_gsm,[accedi per visualizzare l'URL] where scid_gsm.sci...

    €21 (Avg Bid)
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    7 offerte

    Need the google sheet expert for small job.. Please bid if you are the expert. Details will be shared with winning bidder.

    €19 (Avg Bid)
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    6 offerte

    ...- Full copyrights - Proposal needed - Completly tested for all browsers - No upfront payment and i will not set up the milestone before project is complete finished - Onetime payment with 900 Dollar once the project is tested and done for starting I will send the detailed scope document once we are chatting. Build with Asp.net/J2EE and Angular.js or

    €620 (Avg Bid)
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    22 offerte

    I have 1000kg of paper products (letters in envelopes) that have to be delivered from Pakistan to Canada. This is appr...found the cheapest way - I will pay you $50. Only one person - the person that finds the cheapest method - will get paid. Tell me of your shipping method and company in your bid, I will confirm and once I confirm you will get paid.

    €96 (Avg Bid)
    Locale
    €96 Offerta Media
    22 offerte

    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

    €92 (Avg Bid)
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    12 offerte

    I want a content writer who knows digital design or digital electronics and vhdl subjects very well.

    €71 (Avg Bid)
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    21 offerte

    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

    €86 (Avg Bid)
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    2 offerte

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    €17 / hr (Avg Bid)
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    9 offerte
    verilog assignment Terminato left

    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

    €111 (Avg Bid)
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    12 offerte

    Hi we have needed 100 article in English language . this project is a regular basis it means 100 article every month new project. content writing in keyword basis and given topic 100% unique and no Grammarly mistakes not use in any article spinning tool pass of copayscap tool if use any article spinning tool we do not pay any amount. because many

    €127 (Avg Bid)
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    41 offerte
    PRESENT-80 Terminato left

    Hi there! I'm based in Ahmedabad, India. This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project which can be found in section 3.1 of uploaded pdf (round-based based architecture of PRESENT-80). The code has already been developed and I'm getting the proper results as well. But

    €47 (Avg Bid)
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    4 offerte

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found in the pages between 342 to 355. The code has already been developed and I'm getting the proper results as well. But I want to build a clock based design so that I can perform power

    €25 (Avg Bid)
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    2 offerte

    ...platform preferably a light weighted mobile platform which will help the farmers(users) to post minimum bidding propose price (msp) for retailers/ end consumers to know and bid for buying. It will be good if logistic module( carriers who can transport the crops from the source to destination are embedded in the design.... A. Forecast correct price B

    €128 (Avg Bid)
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    3 offerte

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    €3769 (Avg Bid)
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    27 offerte

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    €331 (Avg Bid)
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    3 offerte

    I need a full-time freelance bidder to bid on projects on my behalf. You should also chat with the clients after the bid. You will be given a share of the project bids you won. ONLY BID IF YOU CAN WORK ON SHARE BASIS.

    €3 / hr (Avg Bid)
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    12 offerte

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found in the pages between 342 to 355. The code has already been developed but I'm unable to procure the final result. ( As i can see that the individual modules are successfully executing

    €134 (Avg Bid)
    €134 Offerta Media
    9 offerte

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

    €55 (Avg Bid)
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    18 offerte
    need expert on VHDL Terminato left

    expert on VHDL is need for a project on digital thermostat. This is a simple task. expert only should bid

    €62 (Avg Bid)
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    20 offerte